Fixed bugs, finished BEQ, Added Halt
This commit is contained in:
jose.rodriguezlabra
BIN
lab2CA.runs/synth_1/CPU9bits.dcp
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BIN
lab2CA.runs/synth_1/CPU9bits.dcp
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@@ -17,20 +17,26 @@ proc create_report { reportName command } {
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send_msg_id runtcl-5 warning "$msg"
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}
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}
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set_msg_config -id {Synth 8-256} -limit 10000
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set_msg_config -id {Synth 8-638} -limit 10000
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create_project -in_memory -part xc7k160tifbg484-2L
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set_param project.singleFileAddWarning.threshold 0
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set_param project.compositeFile.enableAutoGeneration 0
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set_param synth.vivado.isSynthRun true
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set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
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set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
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set_property webtalk.parent_dir {C:/Users/JoseIgnacio/CA Lab/lab2CA.cache/wt} [current_project]
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set_property parent.project_path {C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr} [current_project]
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set_property default_lib xil_defaultlib [current_project]
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set_property target_language Verilog [current_project]
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set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
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set_property ip_output_repo {c:/Users/JoseIgnacio/CA Lab/lab2CA.cache/ip} [current_project]
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set_property ip_cache_permissions {read write} [current_project]
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read_verilog -library xil_defaultlib {
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v}
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}
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# Mark all dcp files as not used in implementation to prevent them from being
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# stitched into the results of this synthesis run. Any black boxes in the
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@@ -43,12 +49,12 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
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set_param ips.enableIPCacheLiteLoad 1
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close [open __synthesis_is_running__ w]
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synth_design -top FetchUnit -part xc7k160tifbg484-2L
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synth_design -top CPU9bits -part xc7k160tifbg484-2L
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# disable binary constraint mode for synth run checkpoints
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set_param constraints.enableBinaryConstraints false
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write_checkpoint -force -noxdef FetchUnit.dcp
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create_report "synth_1_synth_report_utilization_0" "report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb"
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write_checkpoint -force -noxdef CPU9bits.dcp
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create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb"
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file delete __synthesis_is_running__
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close [open __synthesis_is_complete__ w]
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341
lab2CA.runs/synth_1/CPU9bits.vds
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341
lab2CA.runs/synth_1/CPU9bits.vds
Normal file
@@ -0,0 +1,341 @@
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#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Wed Mar 13 11:12:14 2019
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# Process ID: 13200
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# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
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# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds
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# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source CPU9bits.tcl -notrace
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Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 18016
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 363.336 ; gain = 101.195
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
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INFO: [Synth 8-6155] done synthesizing module 'decoder' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:774]
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INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:774]
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INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:404]
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INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:409]
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INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:404]
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INFO: [Synth 8-6155] done synthesizing module 'RegFile' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (6#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:333]
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INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339]
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INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (7#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:333]
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INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (8#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:961]
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INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
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INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:684]
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||||
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (9#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:684]
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INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (10#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
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INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (11#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:961]
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INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:721]
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INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (12#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:721]
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INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:640]
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INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (13#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:640]
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INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (14#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:850]
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INFO: [Synth 8-6155] done synthesizing module 'shift_left' (15#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:850]
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||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:887]
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||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (16#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:887]
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||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:924]
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||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (17#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:924]
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||||
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317]
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||||
INFO: [Synth 8-6155] done synthesizing module 'less_than' (18#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317]
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||||
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1075]
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||||
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (19#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1075]
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||||
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:532]
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||||
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:538]
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||||
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (20#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:532]
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||||
WARNING: [Synth 8-3848] Net result_L in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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||||
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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||||
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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||||
WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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INFO: [Synth 8-6155] done synthesizing module 'ALU' (21#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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||||
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (22#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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||||
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:347]
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INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:353]
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||||
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (23#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:347]
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||||
WARNING: [Synth 8-3848] Net dataMemOut in module/entity CPU9bits does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:8]
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INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (24#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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||||
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
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||||
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
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||||
---------------------------------------------------------------------------------
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||||
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051
|
||||
---------------------------------------------------------------------------------
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||||
---------------------------------------------------------------------------------
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||||
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051
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||||
---------------------------------------------------------------------------------
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||||
---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7k160tifbg484-2L
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||||
---------------------------------------------------------------------------------
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||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'regOut_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:269]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'aluOut_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'FU_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:19]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'addi_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:59]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'mem_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:79]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'RegEn_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:18]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'halt_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:89]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.191 ; gain = 158.051
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 144
|
||||
+---Registers :
|
||||
9 Bit Registers := 5
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 2
|
||||
2 Input 9 Bit Muxes := 5
|
||||
4 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
13 Input 3 Bit Muxes := 1
|
||||
13 Input 1 Bit Muxes := 6
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module decoder
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 4 Bit Muxes := 1
|
||||
Module register
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module mux_4_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 1
|
||||
Module add_1bit
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
Module ControlUnit
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 3 Bit Muxes := 2
|
||||
13 Input 3 Bit Muxes := 1
|
||||
13 Input 1 Bit Muxes := 6
|
||||
Module bit1_mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 600 (col length:100)
|
||||
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\CU/halt_reg )
|
||||
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/addi_reg) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/mem_reg) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/RegEn_reg) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/halt_reg) is unused and will be removed from module CPU9bits.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |OBUF | 1|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 1|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 31 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 675.293 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
61 Infos, 31 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 675.293 ; gain = 426.164
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 675.293 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 11:12:35 2019...
|
||||
BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
Normal file
BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
Normal file
Binary file not shown.
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:36:14 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb
|
||||
| Design : FetchUnit
|
||||
| Date : Wed Mar 13 11:12:35 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
| Design : CPU9bits
|
||||
| Device : 7k160tifbg484-2L
|
||||
| Design State : Synthesized
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
@@ -30,11 +30,11 @@ Table of Contents
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 15 | 0 | 101400 | 0.01 |
|
||||
| LUT as Logic | 15 | 0 | 101400 | 0.01 |
|
||||
| Slice LUTs* | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| Slice Registers | 9 | 0 | 202800 | <0.01 |
|
||||
| Register as Flip Flop | 9 | 0 | 202800 | <0.01 |
|
||||
| Slice Registers | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Latch | 0 | 0 | 202800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
|
||||
@@ -57,7 +57,7 @@ Table of Contents
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 9 | Yes | Reset | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -90,7 +90,7 @@ Table of Contents
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 21 | 0 | 285 | 7.37 |
|
||||
| Bonded IOB | 1 | 0 | 285 | 0.35 |
|
||||
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
@@ -117,7 +117,7 @@ Table of Contents
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
@@ -151,16 +151,7 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| IBUF | 12 | IO |
|
||||
| OBUF | 9 | IO |
|
||||
| FDRE | 9 | Flop & Latch |
|
||||
| LUT6 | 6 | LUT |
|
||||
| LUT5 | 5 | LUT |
|
||||
| LUT4 | 5 | LUT |
|
||||
| LUT3 | 2 | LUT |
|
||||
| LUT2 | 1 | LUT |
|
||||
| LUT1 | 1 | LUT |
|
||||
| BUFG | 1 | Clock |
|
||||
| OBUF | 1 | IO |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
Binary file not shown.
@@ -1,261 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Wed Feb 20 11:35:49 2019
|
||||
# Process ID: 8280
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source FetchUnit.tcl -notrace
|
||||
Command: synth_design -top FetchUnit -part xc7k160tifbg484-2L
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 5464
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.242 ; gain = 98.211
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'register' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:53]
|
||||
WARNING: [Synth 8-350] instance 'PCAdder' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:18]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312]
|
||||
WARNING: [Synth 8-689] width (2) of port connection 'switch' does not match port width (1) of module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:28]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
WARNING: [Synth 8-3331] design FetchUnit has unconnected port op_idx[1]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
INFO: [Synth 8-5544] ROM "Dout" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 18
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module register
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module add_1bit
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 600 (col length:100)
|
||||
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-3331] design FetchUnit has unconnected port op_idx[1]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |LUT1 | 1|
|
||||
|3 |LUT2 | 1|
|
||||
|4 |LUT3 | 2|
|
||||
|5 |LUT4 | 5|
|
||||
|6 |LUT5 | 5|
|
||||
|7 |LUT6 | 6|
|
||||
|8 |FDRE | 9|
|
||||
|9 |IBUF | 12|
|
||||
|10 |OBUF | 9|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+---------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+---------+------+
|
||||
|1 |top | | 51|
|
||||
|2 | PC |register | 29|
|
||||
+------+---------+---------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.250 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
19 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 682.250 ; gain = 421.219
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.250 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Feb 20 11:36:14 2019...
|
||||
Binary file not shown.
@@ -1,11 +1,23 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
|
||||
<File Type="PA-TCL" Name="FetchUnit.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="FetchUnit.vds"/>
|
||||
<File Type="RDS-DCP" Name="FetchUnit.dcp"/>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1552489932">
|
||||
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="CPU9bits.vds"/>
|
||||
<File Type="RDS-UTIL" Name="CPU9bits_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="CPU9bits_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="CPU9bits.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="CPU9bits_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -13,6 +25,13 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -20,15 +39,21 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
||||
<File Path="$PSRCDIR/sources_1/new/CPU9bits.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -38,7 +63,7 @@
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="FetchUnit"/>
|
||||
<Option Name="TopModule" Val="CPU9bits"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
|
||||
@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log FetchUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl
|
||||
vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
|
||||
@@ -2,11 +2,11 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Wed Feb 20 11:35:49 2019
|
||||
# Process ID: 8280
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
# Start of session at: Wed Mar 13 11:12:14 2019
|
||||
# Process ID: 13200
|
||||
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source FetchUnit.tcl -notrace
|
||||
source CPU9bits.tcl -notrace
|
||||
|
||||
Binary file not shown.
Reference in New Issue
Block a user