Fixed bugs, finished BEQ, Added Halt

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -270,7 +270,7 @@ module decoder (
             2'b01: regOut <= 4'b0010;
             2'b10: regOut <= 4'b0100;
             2'b11: regOut <= 4'b1000;
-            default: regOut <= 4'bxxxx; 
+            default: regOut <= 4'b0000; 
         endcase 
         end
     end
@@ -344,6 +344,21 @@ module mux_2_1(
     end
 endmodule
 
+module bit1_mux_2_1(
+    input wire switch,
+    input wire A,B,
+    output reg out);
+           
+    always @(A,B,switch) begin
+        case (switch)
+            1'b0 : out = A;
+            1'b1 : out = B;
+            default : out = 1'b1;
+        endcase
+    end
+endmodule
+
+
 //testbench
 module mux_2_1_tb();
     reg s;
@@ -519,7 +534,7 @@ module mux_16_1(
     input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,
     output reg [8:0] out);
            
-    always @(A,B,C,D,E,F,G,H,switch) begin
+    always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin
         case (switch)
             4'b0000 : out = A;
             4'b0001 : out = B;
@@ -949,6 +964,7 @@ module sub_9bit(
     output wire [8:0] C);
     
     wire [8:0] D;
+    wire cout;
     
     twos_compliment_9bit two_comp0(
         .A(B),
@@ -958,7 +974,8 @@ module sub_9bit(
         .A(A),
         .B(D),
         .Cin(1'b0),
-        .Sum(C));
+        .Sum(C),
+        .Cout(cout));
 
 endmodule
 
@@ -1011,6 +1028,7 @@ module twos_compliment_9bit(
     output wire [8:0] B);
     
     wire [8:0] C;
+    wire cout;
     
     not_9bit not0(
         .A(A),
@@ -1020,7 +1038,8 @@ module twos_compliment_9bit(
         .A(C),
         .B(9'b000000000),
         .Cin(1'b1),
-        .Sum(B));
+        .Sum(B),
+        .Cout(cout));
 
 endmodule
 
@@ -1053,7 +1072,7 @@ module twos_compliment_tb();
     end
 endmodule
 
-module zero(
+module BEQ(
     input wire [8:0] A,
     output wire [8:0] B);