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Fixed bugs, finished BEQ, Added Halt

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This commit is contained in:
jose.rodriguezlabra
2019-03-13 11:14:52 -04:00
parent 911d8e31cc
commit 026eb65861
69 changed files with 1145 additions and 1038 deletions
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29
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -2,12 +2,13 @@
module CPU9bits(input wire [8:0] instr,
input wire reset, clk,
output reg done
output wire done
);
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
wire [2:0] FU, aluOp;
wire addiS, RegEn, loadS;
wire [2:0] FU;
wire [3:0] aluOp;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1;
RegFile RF(
.clk(clk),
@@ -24,7 +25,7 @@ module CPU9bits(input wire [8:0] instr,
FetchUnit FetchU(
.clk(clk),
.reset(reset),
.op_idx(FU[0]),
.op_idx(fetchBranch),
.AddrIn(FUAddr),
.AddrOut(PCout)
);
@@ -43,7 +44,8 @@ module CPU9bits(input wire [8:0] instr,
.FU(FU),
.addi(addiS),
.mem(loadS),
.load(loadMux)
.RegEn(RegEn),
.halt(done)
);
@@ -53,7 +55,8 @@ module CPU9bits(input wire [8:0] instr,
.A(PCout),
.B(JBRes),
.Cin(9'b000000000),
.Sum(FUJB));
.Sum(FUJB),
.Cout(cout0));
mux_2_1 mux1(
.A(op1),
@@ -62,18 +65,25 @@ module CPU9bits(input wire [8:0] instr,
.switch(FU[1]));
mux_2_1 mux2(
.A({4'b0000,instr[4:0]}),
.B({6'b000000,instr[2:0]}),
.A({4'b0000,instr[4:0]}), //Jump
.B({6'b000000,instr[2:0]}),//Branch
.out(JBRes),
.switch(FU[2]));
bit1_mux_2_1 BranMux( // BEQ MUX
.A(FU[0]),
.B(op1[0]),
.out(fetchBranch),
.switch(FU[2])); // FU[2] only goes high when BEQ
///--------------------------Addi Stuff
add_9bit Addier(
.A({6'b000000,instr[2:0]}),
.B(op1),
.Cin(9'b000000000),
.Sum(AddiOut));
.Sum(AddiOut),
.Cout(cout1));
mux_2_1 mux3(
.A(AluOut),
@@ -109,6 +119,7 @@ module CPU9bits_tb();
.done(done));
initial begin
#5
reset = 0;
#10
reset = 1;