William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fixed bugs, finished BEQ, Added Halt

Browse Source
This commit is contained in:
jose.rodriguezlabra
2019-03-13 11:14:52 -04:00
parent 911d8e31cc
commit 026eb65861
69 changed files with 1145 additions and 1038 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -7,69 +7,88 @@ module ControlUnit(
output reg [2:0] FU,
output reg addi,
output reg mem,
output reg load,
output reg RegEn);
output reg RegEn,
output reg halt);
always @(instIn)begin
always @(instIn, functBit)begin
case(instIn)
4'b0101:
if(functBit == 1) begin
aluOut <= 4'b0001; //sub
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
else begin
aluOut <= 4'b0000; //Add
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b1101: begin
aluOut <= 4'b0011; //nor
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b1110:
if(functBit == 1) begin
aluOut <= 4'b0100; //and
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
else begin
aluOut <= 4'b0010; //or
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b1111:
if(functBit == 1) begin
aluOut <= 4'b0110; //srl
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
else begin
aluOut <= 4'b0101; //shift left
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b0111: begin
aluOut <= 4'b1001; //Less than
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b0110: begin
addi <= 1'b1; // addi
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b1001: begin
4'b1001: begin //We got it wrong, first bit must always be zero whenever branching happens. Fixed
//FU <= 3'b010; // jump
FU <= 3'b010; // jump
RegEn <= 1'b1;
end
4'b1100: begin
FU <= 3'b011; // branch
4'b1010: begin
//FU <= 3'b011; // branch
FU <= 3'b110; // branch
RegEn <= 1'b1;
end
4'b1000: begin
FU <= 3'b001; // jumpreg
//FU <= 3'b001; // jumpreg
FU <= 3'b000; // jumpreg
RegEn <= 1'b1;
end
4'b0001: begin
mem <= 1'b0; // load
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b0010: begin
mem <= 1'b1; // store
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
end
4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere
halt <= 1'b1; // halt
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
end
default: aluOut <= 4'bxxxx;
endcase
@@ -84,7 +103,6 @@ module ControlUnit_tb();
wire [2:0] FetchUnit;
wire addImmediate;
wire memory;
wire loadIt;
wire RegEnable;
@@ -95,7 +113,6 @@ module ControlUnit_tb();
.FU(FetchUnit),
.addi(addImmediate),
.mem(memory),
.load(loadIt),
.RegEn(RegEnable)
);