Fixed bugs, finished BEQ, Added Halt

2019-03-13 11:14:52 -04:00
parent 911d8e31cc
commit 026eb65861
69 changed files with 1145 additions and 1038 deletions
--- a/lab2CA.srcs/sources_1/new/FetchUnit.v
+++ b/lab2CA.srcs/sources_1/new/FetchUnit.v
@@ -7,6 +7,7 @@ module FetchUnit(input wire clk, reset,
  
    //Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a) 
    wire [8:0] progC_out, result_a, result_m;
+    wire cout;
    
    register PC(
        .clk(clk),
@@ -19,7 +20,8 @@ module FetchUnit(input wire clk, reset,
        .A(progC_out),
        .B(9'b000000001),
        .Cin(9'b000000000),
-        .Sum(AddrOut));
+        .Sum(AddrOut),
+        .Cout(cout));
        
    mux_2_1 PCmux(
        .A(AddrIn),