Set some comments

2019-02-15 12:38:07 -05:00
parent 7aa2cfff2a
commit 0b358a6c41
57 changed files with 3092 additions and 86 deletions
--- a/lab2CA.sim/sim_1/impl/timing/xsim/RegFile_vlog.prj
+++ b/lab2CA.sim/sim_1/impl/timing/xsim/RegFile_vlog.prj
@@ -0,0 +1,6 @@
+# compile verilog/system verilog design source files
+verilog xil_defaultlib  \
+"RegFile_time_impl.v" \
+
+# Do not sort compile order
+nosort