William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fixed P3 mem and other

Browse Source
This commit is contained in:
jose.rodriguezlabra
2019-04-11 21:13:57 -04:00
parent a3064a836b
commit 0b4554a844
10 changed files with 114 additions and 146 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
lab2CA.srcs/sources_1/new/instructionMemory.v
View File

@@ -5,17 +5,20 @@ module instructionMemory(
output reg [8:0] readData
);
reg [8:0] memory [5:0]; // Maximum of 512 memory locations
reg [8:0] memory [8:0]; // Maximum of 512 memory locations
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
initial begin
//Equation Solver
memory[0] <= 9'b000000000;
memory[1] <= 9'b000100000; //load
memory[2] <= 9'b000101000; //load
memory[3] <= 9'b010100010; //add
memory[4] <= 9'b111100000; //shift left
memory[5] <= 9'b111100000; //shift left
memory[0] <= 9'b000000000; //Stall
memory[1] <= 9'b000000000; //Stall
memory[2] <= 9'b011000000; //addi
memory[3] <= 9'b011001001; //addi
memory[4] <= 9'b000100000; //load
memory[5] <= 9'b000101010; //load
memory[6] <= 9'b010100010; //add
memory[7] <= 9'b111100000; //shift left
memory[8] <= 9'b111100000; //shift left
// //Testing all instructions
// memory[6] <= 9'b010100011; //sub