William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Nonsense

Browse Source
This commit is contained in:
Johannes
2019-04-11 19:23:15 -04:00
parent bc9c02322c
commit a3064a836b
52 changed files with 3466 additions and 405 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
lab2CA.cache/wt/webtalk_pa.xml
View File

@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Thu Apr 11 18:35:24 2019">
<application name="pa" timeStamp="Thu Apr 11 19:22:54 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="3e90d71c8f614f9191c5fa413d1d835d" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
<property name="ProjectIteration" value="2" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
@@ -17,14 +17,43 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="CloseProject" value="1" type="JavaHandler"/>
<property name="CloseProject" value="2" type="JavaHandler"/>
<property name="OpenProject" value="1" type="JavaHandler"/>
<property name="RunImplementation" value="1" type="JavaHandler"/>
<property name="RunSchematic" value="1" type="JavaHandler"/>
<property name="SimulationRelaunch" value="6" type="JavaHandler"/>
<property name="SimulationRun" value="1" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
<property name="ZoomIn" value="2" type="JavaHandler"/>
<property name="ZoomOut" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="4" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="1" type="GuiHandlerData"/>
<property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="13" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="7" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="3" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="6" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_IN" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_OUT" value="1" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="2" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="7" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="16" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="5" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="16" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="69" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="20" type="GuiMode"/>

11
lab2CA.runs/.jobs/vrs_config_73.xml Normal file
View File

@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

154
lab2CA.runs/impl_1/CPU9bits.tcl Normal file
View File

@@ -0,0 +1,154 @@
#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
set_msg_config -id {Vivado 12-818} -string {{WARNING: [Vivado 12-818] No files matched 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/Bank_behav1.wcfg'}} -suppress
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-3864-DESKTOP-8QFGS52/incrSyn
create_project -in_memory -part xc7k160tifbg484-2L
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
set_property ip_output_repo C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files -quiet C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp
link_design -top CPU9bits -part xc7k160tifbg484-2L
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force CPU9bits_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
if { [llength [get_debug_cores -quiet] ] > 0 } {
implement_debug_core
}
place_design
write_checkpoint -force CPU9bits_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file CPU9bits_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force CPU9bits_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force CPU9bits_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}

471
lab2CA.runs/impl_1/CPU9bits.vdi Normal file
View File

@@ -0,0 +1,471 @@
#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Thu Apr 11 18:41:54 2019
# Process ID: 10352
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits.tcl -notrace
Command: link_design -top CPU9bits -part xc7k160tifbg484-2L
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 578.137 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 583.707 ; gain = 330.434
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.787 . Memory (MB): peak = 596.723 ; gain = 13.016
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1b0ead489
Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1152.047 ; gain = 555.324
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1249.324 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 13 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.131 . Memory (MB): peak = 1249.324 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.151 . Memory (MB): peak = 1249.324 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.163 . Memory (MB): peak = 1249.324 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.217 . Memory (MB): peak = 1249.324 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.221 . Memory (MB): peak = 1249.324 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 13 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1249.324 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.226 . Memory (MB): peak = 1249.324 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.000 | TNS=0.000 |
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2
Ending PowerOpt Patch Enables Task | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1362.293 ; gain = 0.000
Ending Power Optimization Task | Checksum: 1075be1b4
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.918 . Memory (MB): peak = 1362.293 ; gain = 112.969
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 1075be1b4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1362.293 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1362.293 ; gain = 778.586
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
Command: report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3d9e6472
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1362.293 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15f430561
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1c86a0072
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1c86a0072
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 1c86a0072
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1c86a0072
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.293 ; gain = 0.000
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2 Global Placement | Checksum: 2ac705958
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 2ac705958
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1dbfff5a9
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 21cc4f0ec
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 21cc4f0ec
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 206a7ccd0
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 206a7ccd0
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 206a7ccd0
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 206a7ccd0
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 206a7ccd0
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 206a7ccd0
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 206a7ccd0
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 1f13c29b7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f13c29b7
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
Ending Placer Task | Checksum: 161b453db
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1362.293 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
45 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.293 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.117 . Memory (MB): peak = 1362.293 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1362.293 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1362.293 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: b86b4c57 ConstDB: 0 ShapeSum: a9490784 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 12dabf8e5
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1499.332 ; gain = 137.039
Post Restoration Checksum: NetGraph: 45c7ac9c NumContArr: e7e44c49 Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 12dabf8e5
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1504.012 ; gain = 141.719
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 12dabf8e5
Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1504.012 ; gain = 141.719
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: d6870417
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 658f3c2e
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 52
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: fbcb5761
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 4 Rip-up And Reroute | Checksum: fbcb5761
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: fbcb5761
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: fbcb5761
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 6 Post Hold Fix | Checksum: fbcb5761
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.0201332 %
Global Horizontal Routing Utilization = 0.0294118 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 18.018%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 29.4118%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: fbcb5761
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: fbcb5761
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: b44fe7b0
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1531.199 ; gain = 168.906
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
57 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1531.199 ; gain = 168.906
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1531.199 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1531.199 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
Command: report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
Command: report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
68 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 18:43:05 2019...

BIN
lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb Normal file
View File

Binary file not shown.

15
lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt Normal file
View File

@@ -0,0 +1,15 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:05 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
| Design : CPU9bits
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
---------------------------------------------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints

154
lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt Normal file
View File

@@ -0,0 +1,154 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:05 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
| Design : CPU9bits
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
| Temperature Grade : I
-------------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Clock Region Cell Placement per Global Clock: Region X0Y1
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 120 | 0 | 0 | 0 |
| BUFIO | 0 | 32 | 0 | 0 | 0 |
| BUFMR | 0 | 16 | 0 | 0 | 0 |
| BUFR | 0 | 32 | 0 | 0 | 0 |
| MMCM | 0 | 8 | 0 | 0 | 0 |
| PLL | 0 | 8 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 164 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| src0 | g0 | IBUF/O | None | IOB_X0Y78 | X0Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 163 | 2800 | 46 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 |
| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 1 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| g0 | BUFG/O | n/a | | | | 164 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+------+----+
| | X0 | X1 |
+----+------+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 164 | 0 |
| Y0 | 0 | 0 |
+----+------+----+
7. Clock Region Cell Placement per Global Clock: Region X0Y1
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+
| g0 | n/a | BUFG/O | None | 164 | 0 | 163 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X0Y78 [get_ports clk]
# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_clk_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
#endgroup

74
lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt Normal file
View File

@@ -0,0 +1,74 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:42:32 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
| Design : CPU9bits
| Device : xc7k160ti
-------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 9 |
| Unused register locations in slices containing registers | 61 |
+----------------------------------------------------------+-------+
2. Histogram
------------
+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
| 9 | 8 |
| 16+ | 1 |
+--------+--------------+
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 0 | 0 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 91 | 35 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 72 | 23 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+----------------+-------------------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------+-------------------------+------------------+------------------+----------------+
| clk_IBUF_BUFG | pipe2/Dout_reg[6]_2[0] | reset_IBUF | 5 | 9 |
| clk_IBUF_BUFG | pipe2/Dout_reg[6]_1[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe2/E[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe2/Dout_reg[6]_3[0] | reset_IBUF | 4 | 9 |
| clk_IBUF_BUFG | pipe1/Dout_reg[43]_0[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe1/Dout_reg[1]_0[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe1/Dout_reg[1]_1[0] | reset_IBUF | 2 | 9 |
| clk_IBUF_BUFG | pipe1/E[0] | reset_IBUF | 4 | 9 |
| clk_IBUF_BUFG | | reset_IBUF | 35 | 91 |
+----------------+-------------------------+------------------+------------------+----------------+

BIN
lab2CA.runs/impl_1/CPU9bits_drc_opted.pb Normal file
View File

Binary file not shown.

61
lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt Normal file
View File

@@ -0,0 +1,61 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:42:28 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 3
+----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
12 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
12 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

BIN
lab2CA.runs/impl_1/CPU9bits_drc_routed.pb Normal file
View File

Binary file not shown.

61
lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt Normal file
View File

@@ -0,0 +1,61 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:03 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Fully Routed
------------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 3
+----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
12 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
12 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset.
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

526
lab2CA.runs/impl_1/CPU9bits_io_placed.rpt Normal file
View File

@@ -0,0 +1,526 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:42:32 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_io -file CPU9bits_io_placed.rpt
| Design : CPU9bits
| Device : xc7k160ti
| Speed File : -2L
| Package : fbg484
| Package Version : FINAL 2012-06-26
| Package Pin Delay Version : VERS. 2.0 2012-06-26
-------------------------------------------------------------------------------------------------
IO Information
Table of Contents
-----------------
1. Summary
2. IO Assignments by Package Pin
1. Summary
----------
+---------------+
| Total User IO |
+---------------+
| 12 |
+---------------+
2. IO Assignments by Package Pin
--------------------------------
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| A3 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | |
| A4 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | |
| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A8 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| A9 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| A10 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| A11 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A13 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
| A14 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A15 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A16 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| A18 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
| A20 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
| A21 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA1 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA3 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA4 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA5 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA6 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| AA8 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA9 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA10 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA11 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA13 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA14 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA15 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| AA18 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA19 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA20 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA21 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB1 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB2 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB3 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| AB5 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB6 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB10 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB11 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB12 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB13 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| AB15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB17 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB18 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB20 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB21 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB22 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| B1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | |
| B2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | |
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B5 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | |
| B6 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | |
| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B8 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B10 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B11 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B12 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B13 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| B15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B16 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B17 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B20 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
| B21 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
| B22 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| C3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | |
| C4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | |
| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C8 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| C9 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| C10 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| C11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| C12 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C13 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C14 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C15 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C18 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | |
| C19 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
| C20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| C21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| C22 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| D1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | |
| D2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | |
| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | |
| D6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | |
| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| D9 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| D10 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| D11 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| D12 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D14 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| D15 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | |
| D16 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | |
| D17 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| D18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| D19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
| D20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
| D21 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| D22 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| E3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | |
| E4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | |
| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E8 | | High Range | IO_24_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| E9 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E11 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| E12 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| E13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| E14 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| E15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| E16 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E17 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
| E22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
| F1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | |
| F2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | |
| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | |
| F6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | |
| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F8 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| F9 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| F11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| F12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| F13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| F14 | | High Range | IO_6_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| F15 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
| F16 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
| F19 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
| F20 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
| F21 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
| F22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| G3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | |
| G4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | |
| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| G7 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
| G8 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| G9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| G10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G12 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
| G16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
| G17 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
| G19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| G20 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
| G21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| G22 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
| H1 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | |
| H2 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | |
| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H6 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
| H7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
| H8 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H9 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H10 | | High Range | IO_18_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H12 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| H13 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| H14 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| H15 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| H17 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| H18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
| H19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
| H20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H22 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J4 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | |
| J5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
| J6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
| J7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J16 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
| J17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J19 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
| J20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| J21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
| J22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
| K1 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K2 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | |
| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
| K7 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| K11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| K12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K16 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
| K17 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| K18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| K19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
| K20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| K21 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| K22 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
| L1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L3 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| L5 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
| L7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
| L12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
| L13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L16 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| L18 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
| L19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| L20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| L21 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M1 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M2 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M3 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| M4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| M5 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
| M7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| M11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
| M12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M16 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
| M17 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| M18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M20 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
| M21 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
| M22 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| N1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| N2 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| N3 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| N4 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| N5 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| N12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N17 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
| N18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N20 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
| N21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| N22 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| P1 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| P2 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P4 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| P5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| P6 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
| P7 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
| P8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P16 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| P19 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
| P20 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
| P21 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
| P22 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
| R1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| R2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| R3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| R4 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| R5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| R6 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| R7 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| R16 | reset | High Range | IO_L20P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| R17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| R18 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
| R19 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R21 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
| R22 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
| T1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| T2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| T3 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T5 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| T6 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | |
| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T8 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T9 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T10 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T11 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | |
| T15 | result[2] | High Range | IO_L24P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| T16 | done | High Range | IO_L20N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| T19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T20 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T21 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| U1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| U2 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U3 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U5 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| U6 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| U7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| U8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| U9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| U10 | | High Performance | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| U11 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U15 | result[1] | High Range | IO_L24N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| U16 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| U19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| U20 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
| U21 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| U22 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V2 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| V3 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| V4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| V5 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | |
| V6 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| V7 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| V8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V9 | | High Performance | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| V10 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V14 | result[0] | High Range | IO_25_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| V15 | result[4] | High Range | IO_L23P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| V17 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
| V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| V19 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| V20 | clk | High Range | IO_L11P_T1_SRCC_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V22 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| W1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| W2 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| W3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| W4 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| W5 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| W6 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| W7 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W9 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| W10 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| W11 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| W14 | result[6] | High Range | IO_L22P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W15 | result[3] | High Range | IO_L23N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W16 | result[8] | High Range | IO_L21P_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W19 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W20 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W21 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| W22 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y2 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y3 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y4 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y6 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y7 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y8 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y9 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| Y11 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y12 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y13 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y14 | result[5] | High Range | IO_L22N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y16 | result[7] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| Y17 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y18 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y19 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| Y21 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y22 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.

BIN
lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb Normal file
View File

Binary file not shown.

855
lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt Normal file
View File

@@ -0,0 +1,855 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:04 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Fully Routed
--------------------------------------------------------------------------------------------------------------------------------------------------------------
Report Methodology
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Max violations: <unlimited>
Violations found: 164
+-----------+----------+-----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+-----------------------------+------------+
| TIMING-17 | Warning | Non-clocked sequential cell | 164 |
+-----------+----------+-----------------------------+------------+
2. REPORT DETAILS
-----------------
TIMING-17#1 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#2 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#3 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#4 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#5 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#6 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#7 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#8 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#9 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r0/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#10 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#11 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#12 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#13 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#14 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#15 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#16 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#17 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#18 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r1/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#19 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#20 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#21 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#22 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#23 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#24 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#25 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#26 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#27 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r2/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#28 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#29 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#30 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#31 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#32 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#33 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#34 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#35 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#36 Warning
Non-clocked sequential cell
The clock pin EM/Bank/r3/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#37 Warning
Non-clocked sequential cell
The clock pin EM/dM/memory_reg/CLKARDCLK is not reached by a timing clock
Related violations: <none>
TIMING-17#38 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#39 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#40 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#41 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#42 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#43 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#44 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#45 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#46 Warning
Non-clocked sequential cell
The clock pin FD/FetchU/PC/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#47 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#48 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#49 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#50 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#51 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#52 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#53 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#54 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#55 Warning
Non-clocked sequential cell
The clock pin FD/RF/r0/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#56 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#57 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#58 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#59 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#60 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#61 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#62 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#63 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#64 Warning
Non-clocked sequential cell
The clock pin FD/RF/r1/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#65 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#66 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#67 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#68 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#69 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#70 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#71 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#72 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#73 Warning
Non-clocked sequential cell
The clock pin FD/RF/r2/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#74 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#75 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#76 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#77 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#78 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#79 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#80 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#81 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#82 Warning
Non-clocked sequential cell
The clock pin FD/RF/r3/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#83 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#84 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[10]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#85 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[11]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#86 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[12]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#87 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[13]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#88 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[14]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#89 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[15]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#90 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[16]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#91 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[17]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#92 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[18]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#93 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[19]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#94 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#95 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[20]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#96 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[21]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#97 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[22]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#98 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[23]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#99 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#100 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#101 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[42]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#102 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[43]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#103 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[44]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#104 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[45]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#105 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[46]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#106 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#107 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#108 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#109 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#110 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#111 Warning
Non-clocked sequential cell
The clock pin pipe1/Dout_reg[9]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#112 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#113 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[10]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#114 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[11]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#115 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[12]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#116 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[13]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#117 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[14]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#118 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[15]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#119 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#120 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[25]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#121 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[26]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#122 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[27]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#123 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[28]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#124 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[29]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#125 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#126 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[30]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#127 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[31]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#128 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[32]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#129 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[33]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#130 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[34]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#131 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[35]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#132 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[36]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#133 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[37]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#134 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[38]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#135 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[39]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#136 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#137 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[40]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#138 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[41]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#139 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[42]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#140 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[43]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#141 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[44]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#142 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[45]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#143 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[46]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#144 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[47]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#145 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[48]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#146 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[49]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#147 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#148 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[50]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#149 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[51]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#150 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[52]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#151 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[53]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#152 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[54]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#153 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[55]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#154 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[56]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#155 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[57]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#156 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[58]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#157 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[59]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#158 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#159 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[60]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#160 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[61]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#161 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#162 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#163 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[8]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#164 Warning
Non-clocked sequential cell
The clock pin pipe2/Dout_reg[9]/C is not reached by a timing clock
Related violations: <none>

BIN
lab2CA.runs/impl_1/CPU9bits_opt.dcp Normal file
View File

Binary file not shown.

BIN
lab2CA.runs/impl_1/CPU9bits_placed.dcp Normal file
View File

Binary file not shown.

161
lab2CA.runs/impl_1/CPU9bits_power_routed.rpt Normal file
View File

@@ -0,0 +1,161 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:05 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
| Design : CPU9bits
| Device : xc7k160tifbg484-2L
| Design State : routed
| Grade : industrial
| Process : typical
| Characterization : Production
----------------------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 15.838 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 15.645 |
| Device Static (W) | 0.193 |
| Effective TJA (C/W) | 2.5 |
| Max Ambient (C) | 60.8 |
| Junction Temperature (C) | 64.2 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic | 3.275 | 396 | --- | --- |
| LUT as Logic | 3.190 | 184 | 101400 | 0.18 |
| Register | 0.073 | 163 | 202800 | 0.08 |
| F7/F8 Muxes | 0.007 | 3 | 101400 | <0.01 |
| BUFG | 0.005 | 1 | 32 | 3.13 |
| Others | 0.000 | 5 | --- | --- |
| Signals | 3.308 | 335 | --- | --- |
| Block RAM | 0.061 | 0.5 | 325 | 0.15 |
| I/O | 9.001 | 12 | 285 | 4.21 |
| Static Power | 0.193 | | | |
| Total | 15.838 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 0.950 | 7.112 | 6.993 | 0.120 |
| Vccaux | 1.800 | 0.760 | 0.737 | 0.024 |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 4.263 | 4.262 | 0.001 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 0.950 | 0.008 | 0.005 | 0.003 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.018 | 0.000 | 0.018 |
+-----------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 2.5 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 4.2 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+------------+-----------+
| Name | Power (W) |
+------------+-----------+
| CPU9bits | 15.645 |
| EM | 0.129 |
| Bank | 0.037 |
| r0 | 0.034 |
| r1 | 0.003 |
| dM | 0.091 |
| FD | 4.742 |
| FetchU | 3.925 |
| PC | 3.925 |
| RF | 0.817 |
| r0 | 0.185 |
| r1 | 0.449 |
| r2 | 0.181 |
| r3 | 0.002 |
| pipe1 | 0.848 |
| pipe2 | 0.903 |
+------------+-----------+

BIN
lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb Normal file
View File

Binary file not shown.

BIN
lab2CA.runs/impl_1/CPU9bits_route_status.pb Normal file
View File

Binary file not shown.

11
lab2CA.runs/impl_1/CPU9bits_route_status.rpt Normal file
View File

@@ -0,0 +1,11 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 416 :
# of nets not needing routing.......... : 79 :
# of internally routed nets........ : 79 :
# of routable nets..................... : 337 :
# of fully routed nets............. : 337 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

BIN
lab2CA.runs/impl_1/CPU9bits_routed.dcp Normal file
View File

Binary file not shown.

2
lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb Normal file
View File

@@ -0,0 +1,2 @@
2012.4<EFBFBD>)Timing analysis from Implemented netlist.

173
lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt Normal file
View File

@@ -0,0 +1,173 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:43:05 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
| Design : CPU9bits
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 164 register/latch pins with no clock driven by root clock pin: clk (HIGH)
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 417 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 10 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
NA NA NA NA NA NA NA NA NA NA NA NA
There are no user specified timing constraints.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------

BIN
lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb Normal file
View File

Binary file not shown.

213
lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt Normal file
View File

@@ -0,0 +1,213 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Thu Apr 11 18:42:32 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
| Design : CPU9bits
| Device : 7k160tifbg484-2L
| Design State : Fully Placed
-------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 184 | 0 | 101400 | 0.18 |
| LUT as Logic | 184 | 0 | 101400 | 0.18 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 163 | 0 | 202800 | 0.08 |
| Register as Flip Flop | 163 | 0 | 202800 | 0.08 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 3 | 0 | 50700 | <0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 163 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+--------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+------+-------+-----------+-------+
| Slice | 65 | 0 | 25350 | 0.26 |
| SLICEL | 44 | 0 | | |
| SLICEM | 21 | 0 | | |
| LUT as Logic | 184 | 0 | 101400 | 0.18 |
| using O5 output only | 0 | | | |
| using O6 output only | 144 | | | |
| using O5 and O6 | 40 | | | |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 163 | 0 | 202800 | 0.08 |
| Register driven from within the Slice | 68 | | | |
| Register driven from outside the Slice | 95 | | | |
| LUT in front of the register is unused | 46 | | | |
| LUT in front of the register is used | 49 | | | |
| Unique Control Sets | 9 | | 25350 | 0.04 |
+--------------------------------------------+------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 1 | 0 | 650 | 0.15 |
| RAMB18E1 only | 1 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 600 | 0.00 |
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 12 | 0 | 285 | 4.21 |
| IOB Master Pads | 6 | | | |
| IOB Slave Pads | 5 | | | |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
| PHASER_REF | 0 | 0 | 8 | 0.00 |
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
| IN_FIFO | 0 | 0 | 32 | 0.00 |
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
| IBUFDS | 0 | 0 | 275 | 0.00 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 285 | 0.00 |
| OLOGIC | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 32 | 0.00 |
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
| BUFMRCE | 0 | 0 | 16 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFR | 0 | 0 | 32 | 0.00 |
+------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 163 | Flop & Latch |
| LUT6 | 93 | LUT |
| LUT5 | 52 | LUT |
| LUT3 | 36 | LUT |
| LUT4 | 34 | LUT |
| OBUF | 10 | IO |
| LUT2 | 8 | LUT |
| MUXF7 | 3 | MuxFx |
| IBUF | 2 | IO |
| RAMB18E1 | 1 | Block Memory |
| LUT1 | 1 | LUT |
| BUFG | 1 | Clock |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

188
lab2CA.runs/impl_1/gen_run.xml Normal file
View File

@@ -0,0 +1,188 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1555022469">
<File Type="BITSTR-BMM" Name="CPU9bits_bd.bmm"/>
<File Type="OPT-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="CPU9bits_timing_summary_init.rpt"/>
<File Type="ROUTE-PWR" Name="CPU9bits_power_routed.rpt"/>
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
<File Type="OPT-TIMING" Name="CPU9bits_timing_summary_opted.rpt"/>
<File Type="OPT-DCP" Name="CPU9bits_opt.dcp"/>
<File Type="ROUTE-PWR-SUM" Name="CPU9bits_power_summary_routed.pb"/>
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
<File Type="OPT-DRC" Name="CPU9bits_drc_opted.rpt"/>
<File Type="OPT-HWDEF" Name="CPU9bits.hwdef"/>
<File Type="PWROPT-DCP" Name="CPU9bits_pwropt.dcp"/>
<File Type="PWROPT-DRC" Name="CPU9bits_drc_pwropted.rpt"/>
<File Type="PWROPT-TIMING" Name="CPU9bits_timing_summary_pwropted.rpt"/>
<File Type="PLACE-DCP" Name="CPU9bits_placed.dcp"/>
<File Type="PLACE-IO" Name="CPU9bits_io_placed.rpt"/>
<File Type="PLACE-CLK" Name="CPU9bits_clock_utilization_placed.rpt"/>
<File Type="PLACE-UTIL" Name="CPU9bits_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="CPU9bits_utilization_placed.pb"/>
<File Type="PLACE-CTRL" Name="CPU9bits_control_sets_placed.rpt"/>
<File Type="PLACE-SIMILARITY" Name="CPU9bits_incremental_reuse_placed.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="CPU9bits_incremental_reuse_pre_placed.rpt"/>
<File Type="BG-BGN" Name="CPU9bits.bgn"/>
<File Type="PLACE-TIMING" Name="CPU9bits_timing_summary_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="CPU9bits_postplace_pwropt.dcp"/>
<File Type="BG-BIN" Name="CPU9bits.bin"/>
<File Type="POSTPLACE-PWROPT-TIMING" Name="CPU9bits_timing_summary_postplace_pwropted.rpt"/>
<File Type="PHYSOPT-DCP" Name="CPU9bits_physopt.dcp"/>
<File Type="PHYSOPT-DRC" Name="CPU9bits_drc_physopted.rpt"/>
<File Type="BITSTR-MSK" Name="CPU9bits.msk"/>
<File Type="PHYSOPT-TIMING" Name="CPU9bits_timing_summary_physopted.rpt"/>
<File Type="ROUTE-ERROR-DCP" Name="CPU9bits_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="CPU9bits_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="CPU9bits_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="CPU9bits_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="CPU9bits_drc_routed.pb"/>
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
<File Type="BITSTR-LTX" Name="CPU9bits.ltx"/>
<File Type="ROUTE-DRC-RPX" Name="CPU9bits_drc_routed.rpx"/>
<File Type="BITSTR-MMI" Name="CPU9bits.mmi"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_routed.rpt"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="CPU9bits_methodology_drc_routed.rpx"/>
<File Type="BITSTR-SYSDEF" Name="CPU9bits.sysdef"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="CPU9bits_methodology_drc_routed.pb"/>
<File Type="ROUTE-PWR-RPX" Name="CPU9bits_power_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="CPU9bits_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="CPU9bits_route_status.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="CPU9bits_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-PB" Name="CPU9bits_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMING-RPX" Name="CPU9bits_timing_summary_routed.rpx"/>
<File Type="ROUTE-SIMILARITY" Name="CPU9bits_incremental_reuse_routed.rpt"/>
<File Type="ROUTE-CLK" Name="CPU9bits_clock_utilization_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW" Name="CPU9bits_bus_skew_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW-PB" Name="CPU9bits_bus_skew_routed.pb"/>
<File Type="ROUTE-BUS-SKEW-RPX" Name="CPU9bits_bus_skew_routed.rpx"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="CPU9bits_postroute_physopt.dcp"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="CPU9bits_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="CPU9bits_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="CPU9bits_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="CPU9bits_timing_summary_postroute_physopted.rpx"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="CPU9bits_bus_skew_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="CPU9bits_bus_skew_postroute_physopted.pb"/>
<File Type="BG-BIT" Name="CPU9bits.bit"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="CPU9bits_bus_skew_postroute_physopted.rpx"/>
<File Type="BITSTR-RBT" Name="CPU9bits.rbt"/>
<File Type="BITSTR-NKY" Name="CPU9bits.nky"/>
<File Type="BG-DRC" Name="CPU9bits.drc"/>
<File Type="RDI-RDI" Name="CPU9bits.vdi"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ALU.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/EMModule.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/FDModule.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/WMUdule.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/dataMemory.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/instructionMemory.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/CPU9bits.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CPU9bits"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</GenRun>

9
lab2CA.runs/impl_1/htr.txt Normal file
View File

@@ -0,0 +1,9 @@
REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log CPU9bits.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace

BIN
lab2CA.runs/impl_1/init_design.pb Normal file
View File

Binary file not shown.

BIN
lab2CA.runs/impl_1/opt_design.pb Normal file
View File

Binary file not shown.

BIN
lab2CA.runs/impl_1/place_design.pb Normal file
View File

Binary file not shown.

BIN
lab2CA.runs/impl_1/route_design.pb Normal file
View File

Binary file not shown.

12
lab2CA.runs/impl_1/vivado.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Thu Apr 11 18:41:54 2019
# Process ID: 10352
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits.tcl -notrace

BIN
lab2CA.runs/impl_1/vivado.pb Normal file
View File

Binary file not shown.

BIN
lab2CA.runs/synth_1/CPU9bits.dcp
View File

Binary file not shown.

31
lab2CA.runs/synth_1/CPU9bits.tcl
View File

@@ -17,30 +17,33 @@ proc create_report { reportName command } {
send_msg_id runtcl-5 warning "$msg"
}
}
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-3864-DESKTOP-8QFGS52/incrSyn
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
set_msg_config -id {Vivado 12-818} -string {{WARNING: [Vivado 12-818] No files matched 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/Bank_behav1.wcfg'}} -suppress
create_project -in_memory -part xc7k160tifbg484-2L
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project]
set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project]
set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo {c:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip} [current_project]
set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_verilog -library xil_defaultlib {
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v}
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v
}
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the

273
lab2CA.runs/synth_1/CPU9bits.vds
View File

@@ -2,12 +2,12 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Apr 10 12:49:25 2019
# Process ID: 13540
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
# Start of session at: Thu Apr 11 18:41:11 2019
# Process ID: 10636
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits.tcl -notrace
Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
@@ -15,80 +15,82 @@ Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 17664
INFO: Helper process launched with PID 2264
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 362.465 ; gain = 101.664
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.680 ; gain = 101.758
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'FDModule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:338]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
INFO: [Synth 8-6155] done synthesizing module 'decoder' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:408]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:14]
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6155] done synthesizing module 'FDModule' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
INFO: [Synth 8-6157] synthesizing module 'fDPipReg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
INFO: [Synth 8-6155] done synthesizing module 'fDPipReg' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
INFO: [Synth 8-6157] synthesizing module 'EMModule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:537]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
INFO: [Synth 8-6155] done synthesizing module 'ALU' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:352]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (28#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
INFO: [Synth 8-6155] done synthesizing module 'EMModule' (29#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
INFO: [Synth 8-6157] synthesizing module 'eMPipReg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
INFO: [Synth 8-6155] done synthesizing module 'eMPipReg' (30#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
INFO: [Synth 8-6157] synthesizing module 'WMUdule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
INFO: [Synth 8-6155] done synthesizing module 'WMUdule' (31#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (32#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'FDModule' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:338]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
INFO: [Synth 8-6155] done synthesizing module 'decoder' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:408]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:14]
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6155] done synthesizing module 'FDModule' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
INFO: [Synth 8-6157] synthesizing module 'fDPipReg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
INFO: [Synth 8-6155] done synthesizing module 'fDPipReg' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
INFO: [Synth 8-6157] synthesizing module 'EMModule' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:537]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
INFO: [Synth 8-6155] done synthesizing module 'ALU' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:352]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
INFO: [Synth 8-6155] done synthesizing module 'EMModule' (29#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
INFO: [Synth 8-6157] synthesizing module 'eMPipReg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
INFO: [Synth 8-6155] done synthesizing module 'eMPipReg' (30#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
INFO: [Synth 8-6157] synthesizing module 'WMUdule' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
INFO: [Synth 8-6155] done synthesizing module 'WMUdule' (31#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
INFO: [Synth 8-6157] synthesizing module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:995]
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_2bit' (32#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:995]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (33#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[8]
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[7]
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[50]
@@ -96,21 +98,21 @@ WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[49]
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[48]
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[47]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.672 ; gain = 157.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.672 ; gain = 157.750
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.672 ; gain = 157.750
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 418.434 ; gain = 157.633
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 415.672 ; gain = 157.750
---------------------------------------------------------------------------------
INFO: [Synth 8-223] decloning instance 'EM/SE1' (sign_extend_3bit) to 'EM/SE3'
@@ -125,7 +127,7 @@ Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 162
2 Input 1 Bit XORs := 234
+---Registers :
62 Bit Registers := 1
51 Bit Registers := 1
@@ -133,7 +135,7 @@ Detailed RTL Component Info :
+---RAMs :
909 Bit RAMs := 1
+---Muxes :
2 Input 9 Bit Muxes := 8
2 Input 9 Bit Muxes := 10
4 Input 9 Bit Muxes := 4
2 Input 4 Bit Muxes := 2
4 Input 4 Bit Muxes := 2
@@ -141,7 +143,7 @@ Detailed RTL Component Info :
2 Input 3 Bit Muxes := 2
16 Input 3 Bit Muxes := 1
16 Input 2 Bit Muxes := 1
16 Input 1 Bit Muxes := 7
16 Input 1 Bit Muxes := 9
2 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
@@ -178,7 +180,7 @@ Detailed RTL Component Info :
2 Input 3 Bit Muxes := 2
16 Input 3 Bit Muxes := 1
16 Input 2 Bit Muxes := 1
16 Input 1 Bit Muxes := 7
16 Input 1 Bit Muxes := 9
Module fDPipReg
Detailed RTL Component Info :
+---Registers :
@@ -215,7 +217,7 @@ Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 644.680 ; gain = 386.758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
@@ -252,7 +254,7 @@ No constraint files found.
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 644.680 ; gain = 386.758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
@@ -278,7 +280,7 @@ Report RTL Partitions:
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 644.680 ; gain = 386.758
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -302,7 +304,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
---------------------------------------------------------------------------------
Report Check Netlist:
@@ -315,7 +317,7 @@ Report Check Netlist:
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -327,25 +329,25 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -362,67 +364,64 @@ Report Cell Usage:
| |Cell |Count |
+------+---------+------+
|1 |BUFG | 1|
|2 |LUT1 | 2|
|3 |LUT2 | 9|
|4 |LUT3 | 22|
|5 |LUT4 | 25|
|6 |LUT5 | 42|
|7 |LUT6 | 101|
|8 |MUXF7 | 1|
|2 |LUT1 | 14|
|3 |LUT2 | 8|
|4 |LUT3 | 36|
|5 |LUT4 | 34|
|6 |LUT5 | 52|
|7 |LUT6 | 93|
|8 |MUXF7 | 3|
|9 |RAMB18E1 | 1|
|10 |FDRE | 181|
|10 |FDRE | 163|
|11 |IBUF | 2|
|12 |OBUF | 10|
+------+---------+------+
Report Instance Areas:
+------+-----------+------------+------+
| |Instance |Module |Cells |
+------+-----------+------------+------+
|1 |top | | 397|
|2 | EM |EMModule | 46|
|3 | Bank |RegFile_4 | 45|
|4 | r0 |register_5 | 17|
|5 | r1 |register_6 | 10|
|6 | r2 |register_7 | 9|
|7 | r3 |register_8 | 9|
|8 | dM |dataMemory | 1|
|9 | FD |FDModule | 105|
|10 | CU |ControlUnit | 9|
|11 | FetchU |FetchUnit | 42|
|12 | PC |register_3 | 42|
|13 | RF |RegFile | 54|
|14 | r0 |register | 9|
|15 | r1 |register_0 | 27|
|16 | r2 |register_1 | 9|
|17 | r3 |register_2 | 9|
|18 | W |WMUdule | 18|
|19 | mux5 |mux_2_1 | 18|
|20 | pipe1 |fDPipReg | 154|
|21 | pipe2 |eMPipReg | 61|
+------+-----------+------------+------+
+------+-----------+-----------+------+
| |Instance |Module |Cells |
+------+-----------+-----------+------+
|1 |top | | 417|
|2 | EM |EMModule | 46|
|3 | Bank |RegFile_4 | 45|
|4 | r0 |register_5 | 17|
|5 | r1 |register_6 | 10|
|6 | r2 |register_7 | 9|
|7 | r3 |register_8 | 9|
|8 | dM |dataMemory | 1|
|9 | FD |FDModule | 207|
|10 | FetchU |FetchUnit | 131|
|11 | PC |register_3 | 131|
|12 | RF |RegFile | 76|
|13 | r0 |register | 18|
|14 | r1 |register_0 | 31|
|15 | r2 |register_1 | 18|
|16 | r3 |register_2 | 9|
|17 | pipe1 |fDPipReg | 73|
|18 | pipe2 |eMPipReg | 78|
+------+-----------+-----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 6 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 644.680 ; gain = 386.758
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00 . Memory (MB): peak = 683.723 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.133 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
80 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
82 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 683.723 ; gain = 436.063
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 683.723 ; gain = 0.000
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:26 . Memory (MB): peak = 681.133 ; gain = 425.672
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.133 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed Apr 10 12:50:01 2019...
INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 18:41:41 2019...

BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
View File

Binary file not shown.

32
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
View File

@@ -1,8 +1,8 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Apr 10 12:50:00 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Date : Thu Apr 11 18:41:41 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
| Device : 7k160tifbg484-2L
@@ -30,13 +30,13 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 168 | 0 | 101400 | 0.17 |
| LUT as Logic | 168 | 0 | 101400 | 0.17 |
| Slice LUTs* | 198 | 0 | 101400 | 0.20 |
| LUT as Logic | 198 | 0 | 101400 | 0.20 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 181 | 0 | 202800 | 0.09 |
| Register as Flip Flop | 181 | 0 | 202800 | 0.09 |
| Slice Registers | 163 | 0 | 202800 | 0.08 |
| Register as Flip Flop | 163 | 0 | 202800 | 0.08 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 1 | 0 | 50700 | <0.01 |
| F7 Muxes | 3 | 0 | 50700 | <0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
@@ -57,7 +57,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 181 | Yes | Reset | - |
| 163 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -152,17 +152,17 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 181 | Flop & Latch |
| LUT6 | 101 | LUT |
| LUT5 | 42 | LUT |
| LUT4 | 25 | LUT |
| LUT3 | 22 | LUT |
| FDRE | 163 | Flop & Latch |
| LUT6 | 93 | LUT |
| LUT5 | 52 | LUT |
| LUT3 | 36 | LUT |
| LUT4 | 34 | LUT |
| LUT1 | 14 | LUT |
| OBUF | 10 | IO |
| LUT2 | 9 | LUT |
| LUT1 | 2 | LUT |
| LUT2 | 8 | LUT |
| MUXF7 | 3 | MuxFx |
| IBUF | 2 | IO |
| RAMB18E1 | 1 | Block Memory |
| MUXF7 | 1 | MuxFx |
| BUFG | 1 | Clock |
+----------+------+---------------------+

5
lab2CA.runs/synth_1/gen_run.xml
View File

@@ -1,11 +1,14 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1554914960">
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1555022469">
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
<File Type="RDS-RDS" Name="CPU9bits.vds"/>
<File Type="RDS-UTIL" Name="CPU9bits_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="CPU9bits_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="CPU9bits.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="CPU9bits_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ALU.v">

10
lab2CA.runs/synth_1/vivado.jou
View File

@@ -2,11 +2,11 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Apr 10 12:49:25 2019
# Process ID: 13540
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
# Start of session at: Thu Apr 11 18:41:11 2019
# Process ID: 10636
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits.tcl -notrace

BIN
lab2CA.runs/synth_1/vivado.pb
View File

Binary file not shown.

BIN
lab2CA.sim/sim_1/behav/xsim/xelab.pb
View File

Binary file not shown.

77
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c
View File

@@ -46,45 +46,20 @@ typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_2(char*, char *);
extern void execute_3(char*, char *);
<<<<<<< Updated upstream
extern void execute_183(char*, char *);
extern void execute_456(char*, char *);
extern void execute_457(char*, char *);
extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
extern void execute_454(char*, char *);
extern void execute_455(char*, char *);
extern void execute_189(char*, char *);
extern void execute_220(char*, char *);
extern void execute_221(char*, char *);
extern void execute_222(char*, char *);
extern void execute_223(char*, char *);
extern void execute_224(char*, char *);
extern void execute_225(char*, char *);
extern void execute_226(char*, char *);
extern void execute_227(char*, char *);
extern void execute_228(char*, char *);
extern void execute_229(char*, char *);
extern void execute_230(char*, char *);
extern void execute_7(char*, char *);
extern void execute_8(char*, char *);
extern void execute_209(char*, char *);
extern void execute_211(char*, char *);
extern void execute_212(char*, char *);
=======
extern void execute_240(char*, char *);
extern void execute_609(char*, char *);
extern void execute_610(char*, char *);
extern void execute_611(char*, char *);
extern void execute_612(char*, char *);
extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
extern void execute_246(char*, char *);
extern void execute_601(char*, char *);
extern void execute_602(char*, char *);
extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
extern void execute_603(char*, char *);
extern void execute_604(char*, char *);
extern void execute_605(char*, char *);
extern void execute_606(char*, char *);
extern void execute_607(char*, char *);
extern void execute_608(char*, char *);
extern void execute_609(char*, char *);
extern void execute_610(char*, char *);
extern void execute_247(char*, char *);
extern void execute_248(char*, char *);
extern void execute_249(char*, char *);
@@ -103,11 +78,9 @@ extern void execute_291(char*, char *);
extern void execute_292(char*, char *);
extern void execute_7(char*, char *);
extern void execute_8(char*, char *);
extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
extern void execute_269(char*, char *);
extern void execute_271(char*, char *);
extern void execute_272(char*, char *);
>>>>>>> Stashed changes
extern void execute_11(char*, char *);
extern void execute_250(char*, char *);
extern void execute_251(char*, char *);
@@ -167,37 +140,6 @@ extern void execute_129(char*, char *);
extern void execute_467(char*, char *);
extern void execute_160(char*, char *);
extern void execute_173(char*, char *);
<<<<<<< Updated upstream
extern void execute_435(char*, char *);
extern void execute_436(char*, char *);
extern void execute_437(char*, char *);
extern void execute_438(char*, char *);
extern void execute_439(char*, char *);
extern void execute_440(char*, char *);
extern void execute_441(char*, char *);
extern void execute_442(char*, char *);
extern void execute_443(char*, char *);
extern void execute_444(char*, char *);
extern void execute_445(char*, char *);
extern void execute_446(char*, char *);
extern void execute_447(char*, char *);
extern void execute_448(char*, char *);
extern void execute_449(char*, char *);
extern void execute_450(char*, char *);
extern void execute_451(char*, char *);
extern void execute_185(char*, char *);
extern void execute_186(char*, char *);
extern void execute_187(char*, char *);
extern void execute_458(char*, char *);
extern void execute_459(char*, char *);
extern void execute_460(char*, char *);
extern void execute_461(char*, char *);
extern void execute_462(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
extern void transaction_109(char*, char*, unsigned, unsigned, unsigned);
funcp funcTab[112] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_183, (funcp)execute_456, (funcp)execute_457, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_454, (funcp)execute_455, (funcp)execute_189, (funcp)execute_220, (funcp)execute_221, (funcp)execute_222, (funcp)execute_223, (funcp)execute_224, (funcp)execute_225, (funcp)execute_226, (funcp)execute_227, (funcp)execute_228, (funcp)execute_229, (funcp)execute_230, (funcp)execute_7, (funcp)execute_8, (funcp)execute_209, (funcp)execute_211, (funcp)execute_212, (funcp)execute_11, (funcp)execute_190, (funcp)execute_191, (funcp)execute_23, (funcp)execute_213, (funcp)execute_214, (funcp)execute_215, (funcp)execute_216, (funcp)execute_217, (funcp)execute_218, (funcp)execute_219, (funcp)execute_26, (funcp)execute_36, (funcp)execute_40, (funcp)execute_42, (funcp)execute_231, (funcp)execute_232, (funcp)execute_233, (funcp)execute_234, (funcp)execute_235, (funcp)execute_236, (funcp)execute_237, (funcp)execute_238, (funcp)execute_239, (funcp)execute_240, (funcp)execute_241, (funcp)execute_242, (funcp)execute_243, (funcp)execute_244, (funcp)execute_425, (funcp)execute_427, (funcp)execute_428, (funcp)execute_430, (funcp)execute_431, (funcp)execute_432, (funcp)execute_433, (funcp)execute_434, (funcp)execute_45, (funcp)execute_46, (funcp)execute_360, (funcp)execute_361, (funcp)execute_362, (funcp)execute_363, (funcp)execute_364, (funcp)execute_365, (funcp)execute_289, (funcp)execute_270, (funcp)execute_310, (funcp)execute_311, (funcp)execute_312, (funcp)execute_313, (funcp)execute_314, (funcp)execute_315, (funcp)execute_357, (funcp)execute_358, (funcp)execute_129, (funcp)execute_405, (funcp)execute_160, (funcp)execute_173, (funcp)execute_435, (funcp)execute_436, (funcp)execute_437, (funcp)execute_438, (funcp)execute_439, (funcp)execute_440, (funcp)execute_441, (funcp)execute_442, (funcp)execute_443, (funcp)execute_444, (funcp)execute_445, (funcp)execute_446, (funcp)execute_447, (funcp)execute_448, (funcp)execute_449, (funcp)execute_450, (funcp)execute_451, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_458, (funcp)execute_459, (funcp)execute_460, (funcp)execute_461, (funcp)execute_462, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_109};
const int NumRelocateId= 112;
=======
extern void execute_497(char*, char *);
extern void execute_498(char*, char *);
extern void execute_499(char*, char *);
@@ -219,16 +161,15 @@ extern void execute_514(char*, char *);
extern void execute_242(char*, char *);
extern void execute_243(char*, char *);
extern void execute_244(char*, char *);
extern void execute_611(char*, char *);
extern void execute_612(char*, char *);
extern void execute_613(char*, char *);
extern void execute_614(char*, char *);
extern void execute_615(char*, char *);
extern void execute_616(char*, char *);
extern void execute_617(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
extern void transaction_129(char*, char*, unsigned, unsigned, unsigned);
funcp funcTab[124] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_240, (funcp)execute_609, (funcp)execute_610, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_246, (funcp)execute_601, (funcp)execute_602, (funcp)execute_603, (funcp)execute_604, (funcp)execute_605, (funcp)execute_606, (funcp)execute_607, (funcp)execute_608, (funcp)execute_247, (funcp)execute_248, (funcp)execute_249, (funcp)execute_280, (funcp)execute_281, (funcp)execute_282, (funcp)execute_283, (funcp)execute_284, (funcp)execute_285, (funcp)execute_286, (funcp)execute_287, (funcp)execute_288, (funcp)execute_289, (funcp)execute_290, (funcp)execute_291, (funcp)execute_292, (funcp)execute_7, (funcp)execute_8, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_269, (funcp)execute_271, (funcp)execute_272, (funcp)execute_11, (funcp)execute_250, (funcp)execute_251, (funcp)execute_23, (funcp)execute_273, (funcp)execute_274, (funcp)execute_275, (funcp)execute_276, (funcp)execute_277, (funcp)execute_278, (funcp)execute_279, (funcp)execute_26, (funcp)execute_36, (funcp)execute_40, (funcp)execute_42, (funcp)execute_293, (funcp)execute_294, (funcp)execute_295, (funcp)execute_296, (funcp)execute_297, (funcp)execute_298, (funcp)execute_299, (funcp)execute_300, (funcp)execute_301, (funcp)execute_302, (funcp)execute_303, (funcp)execute_304, (funcp)execute_305, (funcp)execute_306, (funcp)execute_487, (funcp)execute_489, (funcp)execute_490, (funcp)execute_492, (funcp)execute_493, (funcp)execute_494, (funcp)execute_495, (funcp)execute_496, (funcp)execute_45, (funcp)execute_46, (funcp)execute_422, (funcp)execute_423, (funcp)execute_424, (funcp)execute_425, (funcp)execute_426, (funcp)execute_427, (funcp)execute_351, (funcp)execute_332, (funcp)execute_372, (funcp)execute_373, (funcp)execute_374, (funcp)execute_375, (funcp)execute_376, (funcp)execute_377, (funcp)execute_419, (funcp)execute_420, (funcp)execute_129, (funcp)execute_467, (funcp)execute_160, (funcp)execute_173, (funcp)execute_497, (funcp)execute_498, (funcp)execute_499, (funcp)execute_500, (funcp)execute_501, (funcp)execute_502, (funcp)execute_503, (funcp)execute_504, (funcp)execute_505, (funcp)execute_506, (funcp)execute_507, (funcp)execute_508, (funcp)execute_509, (funcp)execute_510, (funcp)execute_511, (funcp)execute_512, (funcp)execute_513, (funcp)execute_514, (funcp)execute_242, (funcp)execute_243, (funcp)execute_244, (funcp)execute_611, (funcp)execute_612, (funcp)execute_613, (funcp)execute_614, (funcp)execute_615, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_129};
extern void transaction_131(char*, char*, unsigned, unsigned, unsigned);
funcp funcTab[124] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_240, (funcp)execute_611, (funcp)execute_612, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_246, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_603, (funcp)execute_604, (funcp)execute_605, (funcp)execute_606, (funcp)execute_607, (funcp)execute_608, (funcp)execute_609, (funcp)execute_610, (funcp)execute_247, (funcp)execute_248, (funcp)execute_249, (funcp)execute_280, (funcp)execute_281, (funcp)execute_282, (funcp)execute_283, (funcp)execute_284, (funcp)execute_285, (funcp)execute_286, (funcp)execute_287, (funcp)execute_288, (funcp)execute_289, (funcp)execute_290, (funcp)execute_291, (funcp)execute_292, (funcp)execute_7, (funcp)execute_8, (funcp)execute_269, (funcp)execute_271, (funcp)execute_272, (funcp)execute_11, (funcp)execute_250, (funcp)execute_251, (funcp)execute_23, (funcp)execute_273, (funcp)execute_274, (funcp)execute_275, (funcp)execute_276, (funcp)execute_277, (funcp)execute_278, (funcp)execute_279, (funcp)execute_26, (funcp)execute_36, (funcp)execute_40, (funcp)execute_42, (funcp)execute_293, (funcp)execute_294, (funcp)execute_295, (funcp)execute_296, (funcp)execute_297, (funcp)execute_298, (funcp)execute_299, (funcp)execute_300, (funcp)execute_301, (funcp)execute_302, (funcp)execute_303, (funcp)execute_304, (funcp)execute_305, (funcp)execute_306, (funcp)execute_487, (funcp)execute_489, (funcp)execute_490, (funcp)execute_492, (funcp)execute_493, (funcp)execute_494, (funcp)execute_495, (funcp)execute_496, (funcp)execute_45, (funcp)execute_46, (funcp)execute_422, (funcp)execute_423, (funcp)execute_424, (funcp)execute_425, (funcp)execute_426, (funcp)execute_427, (funcp)execute_351, (funcp)execute_332, (funcp)execute_372, (funcp)execute_373, (funcp)execute_374, (funcp)execute_375, (funcp)execute_376, (funcp)execute_377, (funcp)execute_419, (funcp)execute_420, (funcp)execute_129, (funcp)execute_467, (funcp)execute_160, (funcp)execute_173, (funcp)execute_497, (funcp)execute_498, (funcp)execute_499, (funcp)execute_500, (funcp)execute_501, (funcp)execute_502, (funcp)execute_503, (funcp)execute_504, (funcp)execute_505, (funcp)execute_506, (funcp)execute_507, (funcp)execute_508, (funcp)execute_509, (funcp)execute_510, (funcp)execute_511, (funcp)execute_512, (funcp)execute_513, (funcp)execute_514, (funcp)execute_242, (funcp)execute_243, (funcp)execute_244, (funcp)execute_613, (funcp)execute_614, (funcp)execute_615, (funcp)execute_616, (funcp)execute_617, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_131};
const int NumRelocateId= 124;
>>>>>>> Stashed changes
void relocate(char *dp)
{

68
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
View File

@@ -1,18 +1,6 @@
<<<<<<< Updated upstream
<<<<<<< Updated upstream
webtalk_init -webtalk_dir C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Thu Apr 11 17:31:39 2019" -context "software_version_and_target_device"
=======
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Thu Apr 11 18:32:16 2019" -context "software_version_and_target_device"
>>>>>>> Stashed changes
=======
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Thu Apr 11 18:31:01 2019" -context "software_version_and_target_device"
>>>>>>> Stashed changes
webtalk_add_data -client project -key date_generated -value "Thu Apr 11 19:22:53 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
@@ -24,65 +12,21 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
<<<<<<< Updated upstream
<<<<<<< Updated upstream
webtalk_add_data -client project -key random_id -value "17336daf-0d92-4f07-b4a4-ff1c52043edb" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "143" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "2594 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment"
=======
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "146" -context "software_version_and_target_device"
=======
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "145" -context "software_version_and_target_device"
>>>>>>> Stashed changes
webtalk_add_data -client project -key project_iteration -value "160" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
<<<<<<< Updated upstream
>>>>>>> Stashed changes
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "50015 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "315 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.14_sec" -context "xsim\\usage"
<<<<<<< Updated upstream
webtalk_add_data -client xsim -key Simulation_Memory -value "8272_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2296267995 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
=======
webtalk_add_data -client xsim -key Simulation_Memory -value "8152_KB" -context "xsim\\usage"
webtalk_transmit -clientid 4257293974 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
>>>>>>> Stashed changes
=======
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key File_Counter -value "12" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "134 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "26 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "418" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "204" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "0.98_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "50208_KB" -context "xsim\\usage"
webtalk_transmit -clientid 1054187896 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
>>>>>>> Stashed changes
webtalk_add_data -client xsim -key Simulation_Time -value "0.09_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6596_KB" -context "xsim\\usage"
webtalk_transmit -clientid 4075045813 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
View File

Binary file not shown.

BIN
lab2CA.sim/sim_1/behav/xsim/xvlog.pb
View File

Binary file not shown.

2
lab2CA.srcs/sources_1/new/CPU9bits.v
View File

@@ -154,7 +154,7 @@ module CPU9bits_tb();
reset = 1'b1;
#10
reset = 1'b0;
#50000
#300
$finish;
end

11
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -6,24 +6,15 @@ module ControlUnit(
output reg [3:0] aluOut,
output reg [2:0] FU,
output reg [1:0] bank,
<<<<<<< Updated upstream
output reg addi, mem, dataMemEn, RegEn, halt, link, js
);
=======
output reg addi, mem, dataMemEn, RegEn, halt, link, js, compare0, compare1
);
>>>>>>> Stashed changes
);
always @(instIn, functBit)
begin
case(instIn)
4'b0000: // Halt/NOP
begin
<<<<<<< Updated upstream
halt <= functBit;
=======
halt <= ~functBit;
>>>>>>> Stashed changes
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;

6
lab2CA.srcs/sources_1/new/dataMemory.v
View File

@@ -6,7 +6,7 @@ module dataMemory(
output reg [8:0] readData
);
reg [8:0] memory [100:0]; // Maximum of 512 memory locations
reg [8:0] memory [1:0]; // Maximum of 512 memory locations
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
initial begin
@@ -15,8 +15,8 @@ module dataMemory(
//Equation Solver Memory
// memory[0] <= 9'b000000001;
// memory[1] <= 9'b000000010;
memory[0] <= 9'b000000001;
memory[1] <= 9'b000000010;

142
lab2CA.srcs/sources_1/new/instructionMemory.v
View File

@@ -5,17 +5,17 @@ module instructionMemory(
output reg [8:0] readData
);
reg [8:0] memory [100:0]; // Maximum of 512 memory locations
reg [8:0] memory [5:0]; // Maximum of 512 memory locations
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
initial begin
// //Equation Solver
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b000100000; //load
// memory[2] <= 9'b000101000; //load
// memory[3] <= 9'b010100010; //add
// memory[4] <= 9'b111100000; //shift left
// memory[5] <= 9'b111100000; //shift left
//Equation Solver
memory[0] <= 9'b000000000;
memory[1] <= 9'b000100000; //load
memory[2] <= 9'b000101000; //load
memory[3] <= 9'b010100010; //add
memory[4] <= 9'b111100000; //shift left
memory[5] <= 9'b111100000; //shift left
// //Testing all instructions
// memory[6] <= 9'b010100011; //sub
@@ -76,69 +76,69 @@ module instructionMemory(
// memory[39] <= 9'b000000000;
//Bubble Sort
memory[0] <= 9'b000000001; // nop
// Setup
memory[1] <= 9'b010000000; // zero $a
memory[2] <= 9'b000100000; // lb $a, $a
memory[3] <= 9'b010001000; // zero $b
memory[4] <= 9'b010010000; // zero $c
memory[5] <= 9'b010011000; // zero $d
memory[6] <= 9'b101001000; // banks $b, $0
memory[7] <= 9'b101001010; // banks $b, $1
memory[8] <= 9'b100100011; // jf EndChk
// Increment current index to compare next pair of values
// Inc:
memory[9] <= 9'b101001001; // bankl $b, $0
memory[10] <= 9'b011001001; // addi $b, 1
memory[11] <= 9'b101001000; // banks $b, $0
// Check if at the end of the array
// EndChk:
memory[12] <= 9'b101001001; // bankl $b, $0
memory[13] <= 9'b011101000; // slt $b, $a
memory[14] <= 9'b110001001; // beq $b, JSC
memory[15] <= 9'b100100001; // jf LoadNext
// JSC:
memory[16] <= 9'b100110100; // jf SwapChk
// Load next values for comparison
// LoadNext:
memory[17] <= 9'b101001001; // bankl $b, $0
memory[18] <= 9'b011001001; // addi $b, 1
memory[19] <= 9'b000110010; // lb $c, $b
memory[20] <= 9'b011001001; // addi $b, 1
memory[21] <= 9'b000111010; // lb $d, $b
// Compare loaded values to see if they need to be swapped
memory[22] <= 9'b101011110; // banks $d, $3
memory[23] <= 9'b011111100; // slt $d, $c
memory[24] <= 9'b110011001; // beq $d, JI
memory[25] <= 9'b100100001; // jf Swap
// JI:
memory[26] <= 9'b101110010; // jb Inc
// Swap values in array
// Swap:
memory[27] <= 9'b101001001; // bankl $b, $0
memory[28] <= 9'b011001001; // addi $b, 1
memory[29] <= 9'b101011111; // bankl $d, $3
memory[30] <= 9'b001011010; // sb $d, $b
memory[31] <= 9'b011001001; // addi $b, 1
memory[32] <= 9'b001010010; // sb $c, $b
memory[33] <= 9'b010001000; // zero $b
memory[34] <= 9'b011001001; // addi $b, 1
memory[35] <= 9'b101001010; // banks $b, $1
memory[36] <= 9'b101111100; // jb Inc
// Check to see if any swaps have been made in the last iteration
// SwapChk:
memory[37] <= 9'b101001011; // bankl $b, $1
memory[38] <= 9'b110001001; // beq $b, JE
memory[39] <= 9'b100100001; // jf Reset
// JE:
memory[40] <= 9'b100100011; // jf End
// Reset:
memory[41] <= 9'b010001000; // zero $b
memory[42] <= 9'b101001000; // banks $b, $0
memory[43] <= 9'b101111011; // jb LoadNext
// End:
memory[44] <= 9'b000000000; // halt
// //Bubble Sort
// memory[0] <= 9'b000000001; // nop
// // Setup
// memory[1] <= 9'b010000000; // zero $a
// memory[2] <= 9'b000100000; // lb $a, $a
// memory[3] <= 9'b010001000; // zero $b
// memory[4] <= 9'b010010000; // zero $c
// memory[5] <= 9'b010011000; // zero $d
// memory[6] <= 9'b101001000; // banks $b, $0
// memory[7] <= 9'b101001010; // banks $b, $1
// memory[8] <= 9'b100100011; // jf EndChk
// // Increment current index to compare next pair of values
// // Inc:
// memory[9] <= 9'b101001001; // bankl $b, $0
// memory[10] <= 9'b011001001; // addi $b, 1
// memory[11] <= 9'b101001000; // banks $b, $0
// // Check if at the end of the array
// // EndChk:
// memory[12] <= 9'b101001001; // bankl $b, $0
// memory[13] <= 9'b011101000; // slt $b, $a
// memory[14] <= 9'b110001001; // beq $b, JSC
// memory[15] <= 9'b100100001; // jf LoadNext
// // JSC:
// memory[16] <= 9'b100110100; // jf SwapChk
// // Load next values for comparison
// // LoadNext:
// memory[17] <= 9'b101001001; // bankl $b, $0
// memory[18] <= 9'b011001001; // addi $b, 1
// memory[19] <= 9'b000110010; // lb $c, $b
// memory[20] <= 9'b011001001; // addi $b, 1
// memory[21] <= 9'b000111010; // lb $d, $b
// // Compare loaded values to see if they need to be swapped
// memory[22] <= 9'b101011110; // banks $d, $3
// memory[23] <= 9'b011111100; // slt $d, $c
// memory[24] <= 9'b110011001; // beq $d, JI
// memory[25] <= 9'b100100001; // jf Swap
// // JI:
// memory[26] <= 9'b101110010; // jb Inc
// // Swap values in array
// // Swap:
// memory[27] <= 9'b101001001; // bankl $b, $0
// memory[28] <= 9'b011001001; // addi $b, 1
// memory[29] <= 9'b101011111; // bankl $d, $3
// memory[30] <= 9'b001011010; // sb $d, $b
// memory[31] <= 9'b011001001; // addi $b, 1
// memory[32] <= 9'b001010010; // sb $c, $b
// memory[33] <= 9'b010001000; // zero $b
// memory[34] <= 9'b011001001; // addi $b, 1
// memory[35] <= 9'b101001010; // banks $b, $1
// memory[36] <= 9'b101111100; // jb Inc
// // Check to see if any swaps have been made in the last iteration
// // SwapChk:
// memory[37] <= 9'b101001011; // bankl $b, $1
// memory[38] <= 9'b110001001; // beq $b, JE
// memory[39] <= 9'b100100001; // jf Reset
// // JE:
// memory[40] <= 9'b100100011; // jf End
// // Reset:
// memory[41] <= 9'b010001000; // zero $b
// memory[42] <= 9'b101001000; // banks $b, $0
// memory[43] <= 9'b101111011; // jb LoadNext
// // End:
// memory[44] <= 9'b000000000; // halt
// Binary Search

20
lab2CA.xpr
View File

@@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="382"/>
<Option Name="WTXSimLaunchSim" Val="395"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -73,6 +73,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/EMModule.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -129,14 +136,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
@@ -211,7 +210,7 @@
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
@@ -224,6 +223,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>