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All current arithmetic and logical operations are now implemented

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WilliamMiceli
2019-02-15 17:51:05 -05:00
parent 456fcf0804
commit 0b71b05c02
1 changed files with 24 additions and 1 deletions
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lab2CA.srcs/sources_1/new/ALU.v
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@@ -11,17 +11,40 @@ module ALU(
wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H; wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H;
// A (000) - Add // A (000) - Add
adder_9bit( add_9bit add0(
.A(operand0), .A(operand0),
.B(operand1), .B(operand1),
.Cin(1'b0), .Cin(1'b0),
.Sum(result_A)); .Sum(result_A));
// B (001) - Subtract // B (001) - Subtract
sub_9bit sub0(
.A(operand0),
.B(operand1),
.C(result_B));
// C (010) - OR // C (010) - OR
or_9bit or0(
.A(operand0),
.B(operand1),
.C(result_C));
// D (011) - NOR // D (011) - NOR
nor_9bit nor0(
.A(operand0),
.B(operand1),
.C(result_D));
// E (100) - AND // E (100) - AND
and_9bit and0(
.A(operand0),
.B(operand1),
.Cin(1'b0),
.Sum(result_E));
// F (101) - Shift Logical Left // F (101) - Shift Logical Left
shift_logical_left sll(
.A(operand0),
.B(result_F));
// G (110) - Shift Logical Right // G (110) - Shift Logical Right
shift_logical_right slr(
.A(operand0),
.B(result_G));
// H (111) // H (111)