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Computer works (kinda)

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jose.rodriguezlabra
2019-03-13 12:51:44 -04:00
parent 026eb65861
commit 11a1d99e92
64 changed files with 809 additions and 422 deletions
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11
lab2CA.runs/.jobs/vrs_config_31.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_32.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_33.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_34.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

11
lab2CA.runs/.jobs/vrs_config_35.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

11
lab2CA.runs/.jobs/vrs_config_36.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

265
lab2CA.runs/impl_1/CPU9bits.vdi
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 11:12:42 2019
# Process ID: 11884
# Start of session at: Wed Mar 13 12:45:23 2019
# Process ID: 13848
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits.vdi
@@ -16,13 +16,13 @@ Design is defaulting to constrset: constrs_1
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 583.273 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 580.660 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 588.785 ; gain = 334.348
link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 586.176 ; gain = 331.543
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -33,53 +33,53 @@ INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.165 . Memory (MB): peak = 592.141 ; gain = 3.355
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.153 . Memory (MB): peak = 588.063 ; gain = 1.887
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 16212f689
Ending Cache Timing Information Task | Checksum: 157c4d2af
Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1080.938 ; gain = 488.797
Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1112.590 ; gain = 524.527
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 16212f689
Phase 1 Retarget | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1175.109 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 16212f689
Phase 2 Constant propagation | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1175.109 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 16212f689
Phase 3 Sweep | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1175.109 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 16212f689
Phase 4 BUFG optimization | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1175.109 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 16212f689
Phase 5 Shift Register Optimization | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1175.109 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 16212f689
Phase 6 Post Processing Netlist | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1175.109 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.082 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
@@ -100,32 +100,32 @@ Opt_design Change Summary
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 16212f689
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1175.109 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1204.980 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 16212f689
Ending Power Optimization Task | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1175.109 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1204.980 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 16212f689
Ending Final Cleanup Task | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1175.109 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 16212f689
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1175.109 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1175.109 ; gain = 586.324
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000
opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1204.980 ; gain = 618.805
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated.
@@ -154,57 +154,127 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1195.590 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9761e0e0
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fb93d5fd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1195.590 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1195.590 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1204.980 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19236f07e
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1beca6fa2
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1226.531 ; gain = 21.551
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1e494ed1a
Phase 1.3 Build Placer Netlist Model | Checksum: 2a829400b
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1226.531 ; gain = 21.551
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1e494ed1a
Phase 1.4 Constrain Clocks/Macros | Checksum: 2a829400b
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
Phase 1 Placer Initialization | Checksum: 1e494ed1a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1226.531 ; gain = 21.551
Phase 1 Placer Initialization | Checksum: 2a829400b
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1226.531 ; gain = 21.551
Phase 2 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.129 ; gain = 0.000
Phase 2 Final Placement Cleanup | Checksum: 1e494ed1a
Phase 2 Global Placement
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed
Ending Placer Task | Checksum: 19236f07e
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 2a829400b
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1228.102 ; gain = 23.121
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2 Global Placement | Checksum: 2105f6932
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1236.750 ; gain = 31.770
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 2105f6932
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1236.750 ; gain = 31.770
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1f49ee005
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1236.750 ; gain = 31.770
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 261f3e987
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1236.750 ; gain = 31.770
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 261f3e987
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1236.750 ; gain = 31.770
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 3 Detail Placement | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1246.945 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Ending Placer Task | Checksum: 134f94256
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
INFO: [Common 17-83] Releasing license: Implementation
38 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
37 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1204.129 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1246.945 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.122 . Memory (MB): peak = 1204.129 ; gain = 0.000
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.131 . Memory (MB): peak = 1246.945 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 1210.254 ; gain = 6.125
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1246.945 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1210.254 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1246.945 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -216,67 +286,66 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: fad50f9e ConstDB: 0 ShapeSum: 9761e0e0 RouteDB: 0
Checksum: PlaceDB: 39656c59 ConstDB: 0 ShapeSum: fb93d5fd RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: ae2d8a92
Phase 1 Build RT Design | Checksum: fe327772
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.336 ; gain = 223.395
Post Restoration Checksum: NetGraph: 87f14705 NumContArr: 263c438d Constraints: 0 Timing: 0
Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 1456.313 ; gain = 209.367
Post Restoration Checksum: NetGraph: 97c7739f NumContArr: 666b03d3 Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: ae2d8a92
Phase 2.1 Fix Topology Constraints | Checksum: fe327772
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1440.074 ; gain = 227.133
Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 1460.750 ; gain = 213.805
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: ae2d8a92
Phase 2.2 Pre Route Cleanup | Checksum: fe327772
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1440.074 ; gain = 227.133
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 6e1873f8
Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 1460.750 ; gain = 213.805
Phase 2 Router Initialization | Checksum: fe327772
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1448.008 ; gain = 235.066
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1467.887 ; gain = 220.941
Phase 3 Initial Routing
Number of Nodes with overlaps = 0
Phase 3 Initial Routing | Checksum: 6e1873f8
Phase 3 Initial Routing | Checksum: 175100130
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Phase 4.1 Global Iteration 0 | Checksum: 6e1873f8
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
Phase 4 Rip-up And Reroute | Checksum: 6e1873f8
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 4 Rip-up And Reroute | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: 6e1873f8
Phase 5 Delay and Skew Optimization | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: 6e1873f8
Phase 6.1 Hold Fix Iter | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
Phase 6 Post Hold Fix | Checksum: 6e1873f8
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 6 Post Hold Fix | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 0 %
Global Vertical Routing Utilization = 0.000156678 %
Global Horizontal Routing Utilization = 0.000426257 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -286,10 +355,10 @@ Router Utilization Summary
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
North Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 0.900901%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
------------------------------
Reporting congestion hotspots
@@ -311,38 +380,38 @@ Direction: West
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: 6e1873f8
Phase 7 Route finalize | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 6e1873f8
Phase 8 Verifying routed nets | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1474.512 ; gain = 227.566
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 6e1873f8
Phase 9 Depositing Routes | Checksum: 122f3f6b5
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1474.512 ; gain = 227.566
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1474.512 ; gain = 227.566
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
50 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
49 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:32 . Memory (MB): peak = 1454.441 ; gain = 244.188
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1454.441 ; gain = 0.000
route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1474.512 ; gain = 227.566
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.512 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1454.441 ; gain = 0.000
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1474.512 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
@@ -364,7 +433,7 @@ INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
61 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
60 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
@@ -377,4 +446,4 @@ INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utili
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 11:13:49 2019...
INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 12:46:34 2019...

2
lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:49 2019
| Date : Wed Mar 13 12:46:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
| Design : CPU9bits

2
lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:49 2019
| Date : Wed Mar 13 12:46:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
| Design : CPU9bits

2
lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:14 2019
| Date : Wed Mar 13 12:46:00 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
| Design : CPU9bits

6
lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:13 2019
| Date : Wed Mar 13 12:45:55 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
| Design : CPU9bits
@@ -37,12 +37,12 @@ Table of Contents
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
1 out of 1 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done.
5 out of 5 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: instr[8], instr[7], instr[6], instr[5], done.
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
1 out of 1 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done.
5 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: instr[8], instr[7], instr[6], instr[5], done.
Related violations: <none>
CFGBVS-1#1 Warning

6
lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:47 2019
| Date : Wed Mar 13 12:46:33 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
| Design : CPU9bits
@@ -37,12 +37,12 @@ Table of Contents
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
1 out of 1 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done.
5 out of 5 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: instr[8], instr[7], instr[6], instr[5], done.
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
1 out of 1 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done.
5 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: instr[8], instr[7], instr[6], instr[5], done.
Related violations: <none>
CFGBVS-1#1 Warning

10
lab2CA.runs/impl_1/CPU9bits_io_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:14 2019
| Date : Wed Mar 13 12:46:00 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_io -file CPU9bits_io_placed.rpt
| Design : CPU9bits
@@ -423,7 +423,7 @@ Table of Contents
| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | |
| T15 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| T15 | instr[6] | High Range | IO_L24P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| T16 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
@@ -445,7 +445,7 @@ Table of Contents
| U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U15 | | High Range | IO_L24N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U15 | instr[5] | High Range | IO_L24N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| U16 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
@@ -467,7 +467,7 @@ Table of Contents
| V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V14 | done | High Range | IO_25_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| V15 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| V15 | instr[8] | High Range | IO_L23P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| V17 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
| V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
@@ -489,7 +489,7 @@ Table of Contents
| W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| W14 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| W15 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| W15 | instr[7] | High Range | IO_L23N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| W16 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |

2
lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:48 2019
| Date : Wed Mar 13 12:46:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
| Design : CPU9bits

BIN
lab2CA.runs/impl_1/CPU9bits_opt.dcp
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BIN
lab2CA.runs/impl_1/CPU9bits_placed.dcp
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70
lab2CA.runs/impl_1/CPU9bits_power_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:48 2019
| Date : Wed Mar 13 12:46:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
| Design : CPU9bits
@@ -30,15 +30,15 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.084 |
| Total On-Chip Power (W) | 0.476 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.000 |
| Device Static (W) | 0.084 |
| Dynamic (W) | 0.389 |
| Device Static (W) | 0.087 |
| Effective TJA (C/W) | 2.5 |
| Max Ambient (C) | 99.8 |
| Junction Temperature (C) | 25.2 |
| Confidence Level | High |
| Max Ambient (C) | 98.8 |
| Junction Temperature (C) | 26.2 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
@@ -49,15 +49,16 @@ Table of Contents
1.1 On-Chip Components
----------------------
+--------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------+-----------+----------+-----------+-----------------+
| Slice Logic | 0.000 | 1 | --- | --- |
| Others | 0.000 | 1 | --- | --- |
| I/O | 0.000 | 1 | 285 | 0.35 |
| Static Power | 0.084 | | | |
| Total | 0.084 | | | |
+--------------+-----------+----------+-----------+-----------------+
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic | 0.003 | 1 | --- | --- |
| LUT as Logic | 0.003 | 1 | 101400 | <0.01 |
| Signals | 0.013 | 5 | --- | --- |
| I/O | 0.373 | 5 | 285 | 1.75 |
| Static Power | 0.087 | | | |
| Total | 0.476 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
@@ -66,11 +67,11 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 0.950 | 0.023 | 0.000 | 0.023 |
| Vccaux | 1.800 | 0.016 | 0.000 | 0.016 |
| Vccint | 0.950 | 0.056 | 0.032 | 0.024 |
| Vccaux | 1.800 | 0.046 | 0.029 | 0.016 |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.171 | 0.170 | 0.001 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
@@ -86,17 +87,17 @@ Table of Contents
1.3 Confidence Level
--------------------
+-----------------------------+------------+------------------------------------------------+--------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+------------------------------------------------+--------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | High | User specified more than 95% of inputs | |
| Internal nodes activity | High | User specified more than 25% of internal nodes | |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | High | | |
+-----------------------------+------------+------------------------------------------------+--------+
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
2. Settings
@@ -131,8 +132,11 @@ Table of Contents
3.1 By Hierarchy
----------------
+------+-----------+
| Name | Power (W) |
+------+-----------+
+----------+-----------+
| Name | Power (W) |
+----------+-----------+
| CPU9bits | 0.389 |
| CU | 0.007 |
+----------+-----------+

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lab2CA.runs/impl_1/CPU9bits_route_status.rpt
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@@ -1,11 +1,11 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 2 :
# of nets not needing routing.......... : 1 :
# of internally routed nets........ : 1 :
# of routable nets..................... : 1 :
# of fully routed nets............. : 1 :
# of logical nets.......................... : 10 :
# of nets not needing routing.......... : 5 :
# of internally routed nets........ : 5 :
# of routable nets..................... : 5 :
# of fully routed nets............. : 5 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

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2
lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:48 2019
| Date : Wed Mar 13 12:46:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
| Design : CPU9bits

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21
lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:14 2019
| Date : Wed Mar 13 12:46:00 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
| Design : CPU9bits
@@ -31,8 +31,8 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 0 | 0 | 101400 | 0.00 |
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
| Slice LUTs | 1 | 0 | 101400 | <0.01 |
| LUT as Logic | 1 | 0 | 101400 | <0.01 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 0 | 0 | 202800 | 0.00 |
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
@@ -67,10 +67,13 @@ Table of Contents
+------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------------------------------------+------+-------+-----------+-------+
| Slice | 0 | 0 | 25350 | 0.00 |
| SLICEL | 0 | 0 | | |
| Slice | 1 | 0 | 25350 | <0.01 |
| SLICEL | 1 | 0 | | |
| SLICEM | 0 | 0 | | |
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
| LUT as Logic | 1 | 0 | 101400 | <0.01 |
| using O5 output only | 0 | | | |
| using O6 output only | 1 | | | |
| using O5 and O6 | 0 | | | |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
@@ -111,7 +114,9 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 1 | 0 | 285 | 0.35 |
| Bonded IOB | 5 | 0 | 285 | 1.75 |
| IOB Master Pads | 2 | | | |
| IOB Slave Pads | 2 | | | |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
@@ -172,7 +177,9 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| IBUF | 4 | IO |
| OBUF | 1 | IO |
| LUT4 | 1 | LUT |
+----------+------+---------------------+

2
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1552489932">
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1552495493">
<File Type="BITSTR-BMM" Name="CPU9bits_bd.bmm"/>
<File Type="OPT-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="CPU9bits_timing_summary_init.rpt"/>

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lab2CA.runs/impl_1/vivado.jou
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 11:12:42 2019
# Process ID: 11884
# Start of session at: Wed Mar 13 12:45:23 2019
# Process ID: 13848
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits.vdi

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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 11:12:14 2019
# Process ID: 13200
# Start of session at: Wed Mar 13 12:44:56 2019
# Process ID: 10868
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds
@@ -15,56 +15,56 @@ Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 18016
INFO: Helper process launched with PID 9000
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 363.336 ; gain = 101.195
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 364.543 ; gain = 101.914
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
INFO: [Synth 8-6155] done synthesizing module 'decoder' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:774]
INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:774]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:404]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:409]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:404]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (6#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:333]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (7#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:333]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (7#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (8#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:961]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:684]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (9#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:684]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (10#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (11#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:961]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:721]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (12#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:721]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:640]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (13#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:640]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:964]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1029]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (9#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (10#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1029]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (11#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:964]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (12#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (13#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (14#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:850]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (15#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:850]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:887]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (16#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:887]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:924]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (17#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:924]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (18#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1075]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (19#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1075]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:532]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:538]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (20#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:532]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (15#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (16#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (17#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (18#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1078]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (19#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1078]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (20#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
WARNING: [Synth 8-3848] Net result_L in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
@@ -73,37 +73,29 @@ WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver.
INFO: [Synth 8-6155] done synthesizing module 'ALU' (21#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (22#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:347]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:353]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (23#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:347]
WARNING: [Synth 8-3848] Net dataMemOut in module/entity CPU9bits does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:8]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (23#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (24#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.887 ; gain = 158.258
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.887 ; gain = 158.258
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.887 ; gain = 158.258
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
WARNING: [Synth 8-327] inferring latch for variable 'regOut_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:269]
WARNING: [Synth 8-327] inferring latch for variable 'aluOut_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17]
WARNING: [Synth 8-327] inferring latch for variable 'FU_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:19]
WARNING: [Synth 8-327] inferring latch for variable 'addi_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:59]
WARNING: [Synth 8-327] inferring latch for variable 'mem_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:79]
WARNING: [Synth 8-327] inferring latch for variable 'RegEn_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:18]
WARNING: [Synth 8-327] inferring latch for variable 'halt_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:89]
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.191 ; gain = 158.051
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.887 ; gain = 158.258
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -123,10 +115,11 @@ Detailed RTL Component Info :
+---Muxes :
4 Input 9 Bit Muxes := 2
2 Input 9 Bit Muxes := 5
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
13 Input 3 Bit Muxes := 1
13 Input 1 Bit Muxes := 6
13 Input 1 Bit Muxes := 4
2 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
@@ -138,6 +131,7 @@ Hierarchical RTL Component report
Module decoder
Detailed RTL Component Info :
+---Muxes :
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
Module register
Detailed RTL Component Info :
@@ -160,7 +154,7 @@ Detailed RTL Component Info :
+---Muxes :
2 Input 3 Bit Muxes := 2
13 Input 3 Bit Muxes := 1
13 Input 1 Bit Muxes := 6
13 Input 1 Bit Muxes := 4
Module bit1_mux_2_1
Detailed RTL Component Info :
+---Muxes :
@@ -182,24 +176,8 @@ No constraint files found.
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\CU/halt_reg )
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[3]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[2]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[1]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[0]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[3]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[2]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[1]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[0]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[2]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[1]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[0]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/addi_reg) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/mem_reg) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/RegEn_reg) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/halt_reg) is unused and will be removed from module CPU9bits.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -212,7 +190,7 @@ No constraint files found.
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004
Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -224,7 +202,7 @@ Report RTL Partitions:
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -248,7 +226,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Report Check Netlist:
@@ -261,7 +239,7 @@ Report Check Netlist:
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Report RTL Partitions:
@@ -273,25 +251,25 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -307,35 +285,38 @@ Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |OBUF | 1|
|1 |LUT4 | 1|
|2 |IBUF | 4|
|3 |OBUF | 1|
+------+-----+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 1|
+------+---------+-------+------+
+------+---------+------------+------+
| |Instance |Module |Cells |
+------+---------+------------+------+
|1 |top | | 6|
|2 | CU |ControlUnit | 1|
+------+---------+------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 31 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
Synthesis finished with 0 errors, 0 critical warnings and 8 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 675.293 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.730 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
61 Infos, 31 Warnings, 0 Critical Warnings and 0 Errors encountered.
60 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 675.293 ; gain = 426.164
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 675.293 ; gain = 0.000
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 681.730 ; gain = 431.730
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.730 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 11:12:35 2019...
INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 12:45:16 2019...

BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
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10
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:12:35 2019
| Date : Wed Mar 13 12:45:16 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
@@ -30,8 +30,8 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 0 | 0 | 101400 | 0.00 |
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
| Slice LUTs* | 1 | 0 | 101400 | <0.01 |
| LUT as Logic | 1 | 0 | 101400 | <0.01 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 0 | 0 | 202800 | 0.00 |
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
@@ -90,7 +90,7 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 1 | 0 | 285 | 0.35 |
| Bonded IOB | 5 | 0 | 285 | 1.75 |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
@@ -151,7 +151,9 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| IBUF | 4 | IO |
| OBUF | 1 | IO |
| LUT4 | 1 | LUT |
+----------+------+---------------------+

2
lab2CA.runs/synth_1/gen_run.xml
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1552489932">
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1552495493">
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>

4
lab2CA.runs/synth_1/vivado.jou
View File

@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 11:12:14 2019
# Process ID: 13200
# Start of session at: Wed Mar 13 12:44:56 2019
# Process ID: 10868
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds

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lab2CA.runs/synth_1/vivado.pb
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