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Computer works (kinda)

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This commit is contained in:
jose.rodriguezlabra
2019-03-13 12:51:44 -04:00
parent 026eb65861
commit 11a1d99e92
64 changed files with 809 additions and 422 deletions
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1
lab2CA.srcs/sources_1/new/ALU.v
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@@ -11,6 +11,7 @@ module ALU(
wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P;
wire cout;
// A (0000) - Add
add_9bit add0(
.A(operand0),
.B(operand1),

17
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -264,14 +264,17 @@ module decoder (
output reg [3:0] regOut);
always @(en, index)begin
if(en == 1)begin
if(en == 0)begin
case(index)
2'b00: regOut <= 4'b0001;
2'b01: regOut <= 4'b0010;
2'b10: regOut <= 4'b0100;
2'b11: regOut <= 4'b1000;
default: regOut <= 4'b0000;
endcase
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
end
else begin
regOut <= 4'b1111;
end
end
endmodule

28
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -2,14 +2,15 @@
module CPU9bits(input wire [8:0] instr,
input wire reset, clk,
output wire done
output wire done,
output wire [8:0] reg0
);
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
wire [2:0] FU;
wire [3:0] aluOp;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1;
RegFile RF(
.clk(clk),
.reset(reset),
@@ -54,7 +55,7 @@ module CPU9bits(input wire [8:0] instr,
add_9bit JBAdder(
.A(PCout),
.B(JBRes),
.Cin(9'b000000000),
.Cin(1'b0),
.Sum(FUJB),
.Cout(cout0));
@@ -81,7 +82,7 @@ module CPU9bits(input wire [8:0] instr,
add_9bit Addier(
.A({6'b000000,instr[2:0]}),
.B(op1),
.Cin(9'b000000000),
.Cin(1'b0),
.Sum(AddiOut),
.Cout(cout1));
@@ -93,7 +94,7 @@ module CPU9bits(input wire [8:0] instr,
mux_2_1 mux4(
.A(loadMux),
.B(dataMemOut),
.B(9'b000000001),
.out(RFIn),
.switch(loadS));
@@ -119,22 +120,21 @@ module CPU9bits_tb();
.done(done));
initial begin
#5
reset = 0;
reset = 1'b1;
#10
reset = 1;
reset = 1'b0;
#10
instruction = 000100000;
instruction = 9'b000100000;
#10
instruction = 000101001;
instruction = 9'b000101000;
#10
instruction = 010100010;
instruction = 9'b010100010;
#10
instruction = 111100000;
instruction = 9'b111100000;
#10
instruction = 111100000;
instruction = 9'b111100000;
#10
instruction = 000000000;
instruction = 9'b000000000;
#10
$finish;

68
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -16,81 +16,133 @@ module ControlUnit(
if(functBit == 1) begin
aluOut <= 4'b0001; //sub
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
FU <= 3'b001;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
else begin
aluOut <= 4'b0000; //Add
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b1101: begin
aluOut <= 4'b0011; //nor
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b1110:
if(functBit == 1) begin
aluOut <= 4'b0100; //and
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
else begin
aluOut <= 4'b0010; //or
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b1111:
if(functBit == 1) begin
aluOut <= 4'b0110; //srl
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
else begin
aluOut <= 4'b0101; //shift left
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b0111: begin
aluOut <= 4'b1001; //Less than
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b0110: begin
aluOut <= 4'b0000;
addi <= 1'b1; // addi
RegEn <= 1'b0;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
end
4'b1001: begin //We got it wrong, first bit must always be zero whenever branching happens. Fixed
//FU <= 3'b010; // jump
aluOut <= 4'b0000;
FU <= 3'b010; // jump
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b1010: begin
//FU <= 3'b011; // branch
aluOut <= 4'b0000;
FU <= 3'b110; // branch
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b1000: begin
//FU <= 3'b001; // jumpreg
aluOut <= 4'b0000;
FU <= 3'b000; // jumpreg
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b0001: begin
mem <= 1'b0; // load
aluOut <= 4'b0000;
mem <= 1'b1; // load
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
end
4'b0010: begin
mem <= 1'b1; // store
aluOut <= 4'b0000;
mem <= 1'b0; // store
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
end
4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere
halt <= 1'b1; // halt
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
end
default: aluOut <= 4'bxxxx;
default: begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
end
endcase
end
endmodule

2
lab2CA.srcs/sources_1/new/FetchUnit.v
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@@ -19,7 +19,7 @@ module FetchUnit(input wire clk, reset,
add_9bit PCAdder(
.A(progC_out),
.B(9'b000000001),
.Cin(9'b000000000),
.Cin(1'b0),
.Sum(AddrOut),
.Cout(cout));