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Computer works (kinda)

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This commit is contained in:
jose.rodriguezlabra
2019-03-13 12:51:44 -04:00
parent 026eb65861
commit 11a1d99e92
64 changed files with 809 additions and 422 deletions
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28
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -2,14 +2,15 @@
module CPU9bits(input wire [8:0] instr,
input wire reset, clk,
output wire done
output wire done,
output wire [8:0] reg0
);
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
wire [2:0] FU;
wire [3:0] aluOp;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1;
RegFile RF(
.clk(clk),
.reset(reset),
@@ -54,7 +55,7 @@ module CPU9bits(input wire [8:0] instr,
add_9bit JBAdder(
.A(PCout),
.B(JBRes),
.Cin(9'b000000000),
.Cin(1'b0),
.Sum(FUJB),
.Cout(cout0));
@@ -81,7 +82,7 @@ module CPU9bits(input wire [8:0] instr,
add_9bit Addier(
.A({6'b000000,instr[2:0]}),
.B(op1),
.Cin(9'b000000000),
.Cin(1'b0),
.Sum(AddiOut),
.Cout(cout1));
@@ -93,7 +94,7 @@ module CPU9bits(input wire [8:0] instr,
mux_2_1 mux4(
.A(loadMux),
.B(dataMemOut),
.B(9'b000000001),
.out(RFIn),
.switch(loadS));
@@ -119,22 +120,21 @@ module CPU9bits_tb();
.done(done));
initial begin
#5
reset = 0;
reset = 1'b1;
#10
reset = 1;
reset = 1'b0;
#10
instruction = 000100000;
instruction = 9'b000100000;
#10
instruction = 000101001;
instruction = 9'b000101000;
#10
instruction = 010100010;
instruction = 9'b010100010;
#10
instruction = 111100000;
instruction = 9'b111100000;
#10
instruction = 111100000;
instruction = 9'b111100000;
#10
instruction = 000000000;
instruction = 9'b000000000;
#10
$finish;