Created CPU9bits file

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -0,0 +1,43 @@
+`timescale 1ns / 1ps
+
+module CPU9bits(input wire [8:0] instr,
+            input wire reset, clk,
+            output reg done
+    );
+    
+    wire [8:0] op1, op2;
+    
+    RegFile RF(
+        .clk(clk),
+        .reset(reset),
+        .enable(),
+        .write_index(),
+        .op0_idx(),
+        .op1_idx(),
+        .write_data(),
+        .op0(op0),
+        .op1(op1)
+    );
+    
+    FetchUnit FU(
+        .clk(clk),
+        .reset(reset),
+        .op_idx(),
+        .AddrIn(),
+        .AddrOut()
+     );
+     
+     ALU alu(
+        .opcode(),
+        .operand0(op0),
+        .operand1(op1),
+        .result()     
+     );
+     
+     //Make control unit here
+     
+     
+     
+     //------------------------------
+         
+endmodule

lab2CA.srcs/sources_1/new/RegFile.v

@@ -16,6 +16,7 @@ module RegFile(input wire clk, reset, enable,
         .regOut(decOut)
     );
     
+    
     register r0(
         .clk(clk),
         .reset(reset),