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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

Browse Source 
# Conflicts:
#	regFile_tb_behav.wcfg
This commit is contained in:
jose.rodriguezlabra
2019-03-10 13:00:12 -04:00
parent 4c19de70bc c047c801aa
commit 8a903ebcfd
32 changed files with 1093 additions and 924 deletions
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6
.gitignore vendored
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@@ -84,3 +84,9 @@
!*.elf
!*.bmm
!*.xmp
########
# Custom
########
# We want markdown files
!*.md

17
README.md Normal file
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@@ -0,0 +1,17 @@
# ECE 3570 Lab
## Fixes To Be Implemented
* Get rid of the double zero for the enable on the registers
* Make decoder for it
* Redo simulations with other registers using internal signals
* Fix simulation waveforms for Registers, as we are currently changing inputs too quickly (multiple times within a clock cycle)
* Only two registers are being written to, first two within simulation is not being written to
* Need to allow for signed numbers
* Remove subtraction from ALU
* Have arithmetic shift left and right
* <strike>Uncomment all testbenches</strike> (We can have multiple testbenches active at once)
* Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only
* Comparator needed
* Make subtraction more efficient
* Need to verify that FetchUnit is working properly as Martin had some concerns that it probably wasn't functioning properly

35
lab2CA.cache/wt/webtalk_pa.xml
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@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Wed Feb 20 11:35:47 2019">
<application name="pa" timeStamp="Thu Feb 21 15:07:11 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/>
<property name="ProjectIteration" value="7" type="ProjectIteration"/>
@@ -24,54 +24,54 @@ This means code written to parse this file will need to be revisited each subseq
<property name="RunSchematic" value="9" type="JavaHandler"/>
<property name="RunSynthesis" value="16" type="JavaHandler"/>
<property name="SetSourceEnabled" value="2" type="JavaHandler"/>
<property name="SetTopNode" value="22" type="JavaHandler"/>
<property name="SetTopNode" value="23" type="JavaHandler"/>
<property name="ShowView" value="9" type="JavaHandler"/>
<property name="SimulationClose" value="4" type="JavaHandler"/>
<property name="SimulationRun" value="62" type="JavaHandler"/>
<property name="SimulationRun" value="63" type="JavaHandler"/>
<property name="ToggleSelectAreaMode" value="2" type="JavaHandler"/>
<property name="ToolsSettings" value="1" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="2" type="JavaHandler"/>
<property name="ZoomFit" value="6" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="12" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="13" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="65" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="4" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="122" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="142" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="12" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="10" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="119" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="121" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="26" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="27" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="40" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="28" type="GuiHandlerData"/>
<property name="HCodeEditor_BLANK_OPERATIONS" value="5" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="3" type="GuiHandlerData"/>
<property name="HCodeEditor_COMMANDS_TO_FOLD_TEXT" value="3" type="GuiHandlerData"/>
<property name="HCodeEditor_DIFF_WITH" value="3" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="5" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="7" type="GuiHandlerData"/>
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="13" type="GuiHandlerData"/>
<property name="LaunchPanel_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="22" type="GuiHandlerData"/>
<property name="OpenFileAction_OK" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="25" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="26" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RELOAD_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SELECT_AREA" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="23" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="60" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="24" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="61" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_FUNCTIONAL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_TIMING" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_SETTINGS" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_ENABLE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_FIT" value="6" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="6" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="40" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="41" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="9" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="3" type="GuiHandlerData"/>
<property name="ProgressDialog_CANCEL" value="4" type="GuiHandlerData"/>
@@ -85,14 +85,19 @@ This means code written to parse this file will need to be revisited each subseq
<property name="SaveProjectUtils_SAVE" value="5" type="GuiHandlerData"/>
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="12" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="3" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="26" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="27" type="GuiHandlerData"/>
<property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="3" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="17" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="148" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="61" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="60" type="TclMode"/>
</item>
</section>
</application>
</document>

65
lab2CA.runs/impl_1/gen_run.xml
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@@ -1,74 +1,55 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
<File Type="BITSTR-BMM" Name="FetchUnit_bd.bmm"/>
<File Type="OPT-METHODOLOGY-DRC" Name="FetchUnit_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="FetchUnit_timing_summary_init.rpt"/>
<File Type="ROUTE-PWR" Name="FetchUnit_power_routed.rpt"/>
<File Type="PA-TCL" Name="FetchUnit.tcl"/>
<File Type="OPT-TIMING" Name="FetchUnit_timing_summary_opted.rpt"/>
<File Type="OPT-DCP" Name="FetchUnit_opt.dcp"/>
<File Type="ROUTE-PWR-SUM" Name="FetchUnit_power_summary_routed.pb"/>
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="OPT-DRC" Name="FetchUnit_drc_opted.rpt"/>
<File Type="OPT-HWDEF" Name="FetchUnit.hwdef"/>
<File Type="PWROPT-DCP" Name="FetchUnit_pwropt.dcp"/>
<File Type="PWROPT-DRC" Name="FetchUnit_drc_pwropted.rpt"/>
<File Type="PWROPT-TIMING" Name="FetchUnit_timing_summary_pwropted.rpt"/>
<File Type="PLACE-DCP" Name="FetchUnit_placed.dcp"/>
<File Type="PLACE-IO" Name="FetchUnit_io_placed.rpt"/>
<File Type="PLACE-CLK" Name="FetchUnit_clock_utilization_placed.rpt"/>
<File Type="PLACE-UTIL" Name="FetchUnit_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="FetchUnit_utilization_placed.pb"/>
<File Type="PLACE-CTRL" Name="FetchUnit_control_sets_placed.rpt"/>
<File Type="PLACE-SIMILARITY" Name="FetchUnit_incremental_reuse_placed.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="FetchUnit_incremental_reuse_pre_placed.rpt"/>
<File Type="BG-BGN" Name="FetchUnit.bgn"/>
<File Type="PLACE-TIMING" Name="FetchUnit_timing_summary_placed.rpt"/>
<File Type="PWROPT-DCP" Name="FetchUnit_pwropt.dcp"/>
<File Type="PLACE-DCP" Name="FetchUnit_placed.dcp"/>
<File Type="PLACE-PRE-SIMILARITY" Name="FetchUnit_incremental_reuse_pre_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="FetchUnit_postplace_pwropt.dcp"/>
<File Type="BG-BIN" Name="FetchUnit.bin"/>
<File Type="POSTPLACE-PWROPT-TIMING" Name="FetchUnit_timing_summary_postplace_pwropted.rpt"/>
<File Type="PHYSOPT-DCP" Name="FetchUnit_physopt.dcp"/>
<File Type="PHYSOPT-DRC" Name="FetchUnit_drc_physopted.rpt"/>
<File Type="BITSTR-MSK" Name="FetchUnit.msk"/>
<File Type="PHYSOPT-TIMING" Name="FetchUnit_timing_summary_physopted.rpt"/>
<File Type="ROUTE-ERROR-DCP" Name="FetchUnit_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="FetchUnit_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="FetchUnit_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="FetchUnit_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="FetchUnit_drc_routed.pb"/>
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
<File Type="BITSTR-LTX" Name="FetchUnit.ltx"/>
<File Type="ROUTE-DRC-RPX" Name="FetchUnit_drc_routed.rpx"/>
<File Type="BITSTR-MMI" Name="FetchUnit.mmi"/>
<File Type="BITSTR-LTX" Name="FetchUnit.ltx"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="FetchUnit_methodology_drc_routed.rpt"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="FetchUnit_methodology_drc_routed.rpx"/>
<File Type="BITSTR-SYSDEF" Name="FetchUnit.sysdef"/>
<File Type="BITSTR-MMI" Name="FetchUnit.mmi"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="FetchUnit_methodology_drc_routed.pb"/>
<File Type="ROUTE-PWR-RPX" Name="FetchUnit_power_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="FetchUnit_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="FetchUnit_route_status.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="FetchUnit_timing_summary_routed.rpt"/>
<File Type="BITSTR-SYSDEF" Name="FetchUnit.sysdef"/>
<File Type="ROUTE-TIMING-PB" Name="FetchUnit_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMING-RPX" Name="FetchUnit_timing_summary_routed.rpx"/>
<File Type="ROUTE-SIMILARITY" Name="FetchUnit_incremental_reuse_routed.rpt"/>
<File Type="ROUTE-CLK" Name="FetchUnit_clock_utilization_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW" Name="FetchUnit_bus_skew_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW-PB" Name="FetchUnit_bus_skew_routed.pb"/>
<File Type="ROUTE-BUS-SKEW-RPX" Name="FetchUnit_bus_skew_routed.rpx"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="FetchUnit_postroute_physopt.dcp"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="FetchUnit_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="FetchUnit_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="FetchUnit_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="FetchUnit_timing_summary_postroute_physopted.rpx"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="FetchUnit_bus_skew_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="FetchUnit_bus_skew_postroute_physopted.pb"/>
<File Type="BG-BIT" Name="FetchUnit.bit"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="FetchUnit_bus_skew_postroute_physopted.rpx"/>
<File Type="BITSTR-RBT" Name="FetchUnit.rbt"/>
<File Type="BITSTR-NKY" Name="FetchUnit.nky"/>
<File Type="BG-DRC" Name="FetchUnit.drc"/>
<File Type="ROUTE-CLK" Name="FetchUnit_clock_utilization_routed.rpt"/>
<File Type="RDI-RDI" Name="FetchUnit.vdi"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<File Type="OPT-DRC" Name="FetchUnit_drc_opted.rpt"/>
<File Type="PLACE-UTIL" Name="FetchUnit_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="FetchUnit_utilization_placed.pb"/>
<File Type="PLACE-IO" Name="FetchUnit_io_placed.rpt"/>
<File Type="PLACE-CTRL" Name="FetchUnit_control_sets_placed.rpt"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="FetchUnit_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-RPX" Name="FetchUnit_timing_summary_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="FetchUnit_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="FetchUnit_route_status.pb"/>
<File Type="ROUTE-PWR-RPX" Name="FetchUnit_power_routed.rpx"/>
<File Type="ROUTE-DRC" Name="FetchUnit_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="FetchUnit_drc_routed.pb"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="FetchUnit_methodology_drc_routed.rpx"/>
<File Type="ROUTE-BUS-SKEW" Name="FetchUnit_bus_skew_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW-RPX" Name="FetchUnit_bus_skew_routed.rpx"/>
<File Type="ROUTE-BUS-SKEW-PB" Name="FetchUnit_bus_skew_routed.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">

5
lab2CA.runs/synth_1/gen_run.xml
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@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
<File Type="PA-TCL" Name="FetchUnit.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="FetchUnit_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="RDS-RDS" Name="FetchUnit.vds"/>
<File Type="RDS-DCP" Name="FetchUnit.dcp"/>
<File Type="RDS-UTIL" Name="FetchUnit_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="FetchUnit_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="FetchUnit.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="FetchUnit_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="FetchUnit_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">

11
lab2CA.sim/sim_1/behav/xsim/decoder_tb.tcl Normal file
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@@ -0,0 +1,11 @@
set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

9
lab2CA.sim/sim_1/behav/xsim/decoder_tb_vlog.prj Normal file
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@@ -0,0 +1,9 @@
# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort

4
lab2CA.sim/sim_1/behav/xsim/webtalk.jou
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@@ -2,8 +2,8 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Feb 20 11:30:13 2019
# Process ID: 10344
# Start of session at: Wed Feb 27 11:47:34 2019
# Process ID: 6784
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log

12
lab2CA.sim/sim_1/behav/xsim/webtalk_11568.backup.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Feb 20 10:48:52 2019
# Process ID: 11568
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_11844.backup.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Feb 20 10:53:42 2019
# Process ID: 11844
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace

4
lab2CA.sim/sim_1/behav/xsim/webtalk_5680.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou
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@@ -2,8 +2,8 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 17:35:22 2019
# Process ID: 5680
# Start of session at: Wed Feb 27 11:43:09 2019
# Process ID: 1408
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log

8
lab2CA.sim/sim_1/behav/xsim/webtalk_11820.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou
View File

@@ -2,11 +2,11 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 17:37:48 2019
# Process ID: 11820
# Start of session at: Wed Feb 27 11:39:16 2019
# Process ID: 14864
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_16620.backup.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Thu Feb 21 14:46:02 2019
# Process ID: 16620
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/REPOSITORIES/Educational/Western -notrace

8
lab2CA.sim/sim_1/behav/xsim/webtalk_13504.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou
View File

@@ -2,11 +2,11 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Feb 20 11:27:03 2019
# Process ID: 13504
# Start of session at: Wed Feb 27 11:36:59 2019
# Process ID: 7276
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace

BIN
lab2CA.sim/sim_1/behav/xsim/xelab.pb
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1
lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/Compile_Options.txt Normal file
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@@ -0,0 +1 @@
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "decoder_tb_behav" "xil_defaultlib.decoder_tb" "xil_defaultlib.glbl" -log "elaborate.log"

1
lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/TempBreakPointFile.txt Normal file
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@@ -0,0 +1 @@
Breakpoint File Version 1.0

108
lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/obj/xsim_1.c Normal file
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@@ -0,0 +1,108 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_4(char*, char *);
extern void execute_9(char*, char *);
extern void execute_10(char*, char *);
extern void execute_11(char*, char *);
extern void execute_3(char*, char *);
extern void execute_6(char*, char *);
extern void execute_7(char*, char *);
extern void execute_8(char*, char *);
extern void execute_12(char*, char *);
extern void execute_13(char*, char *);
extern void execute_14(char*, char *);
extern void execute_15(char*, char *);
extern void execute_16(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[14] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 14;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/decoder_tb_behav/xsim.reloc", (void **)funcTab, 14);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/decoder_tb_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/decoder_tb_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/decoder_tb_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/decoder_tb_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/decoder_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

44
lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml Normal file
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@@ -0,0 +1,44 @@
<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Wed Feb 27 11:39:16 2019'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2405991" description="" />
<keyValuePair key="date_generated" value="Wed Feb 27 11:39:15 2019" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
<keyValuePair key="project_iteration" value="2" description="" />
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
<keyValuePair key="route_design" value="FALSE" description="" />
<keyValuePair key="target_device" value="not_applicable" description="" />
<keyValuePair key="target_family" value="not_applicable" description="" />
<keyValuePair key="target_package" value="not_applicable" description="" />
<keyValuePair key="target_speed" value="not_applicable" description="" />
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
</section>
<section name="user_environment" level="1" order="2" description="">
<keyValuePair key="cpu_name" value="Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" description="" />
<keyValuePair key="cpu_speed" value="3492 MHz" description="" />
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
<keyValuePair key="system_ram" value="34.000 GB" description="" />
<keyValuePair key="total_processors" value="1" description="" />
</section>
<section name="vivado_usage" level="1" order="3" description="">
</section>
<section name="xsim" level="1" order="4" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="command" value="xsim" description="" />
</section>
<section name="usage" level="2" order="2" description="">
<keyValuePair key="iteration" value="0" description="" />
<keyValuePair key="runtime" value="30 ns" description="" />
<keyValuePair key="simulation_memory" value="6624_KB" description="" />
<keyValuePair key="simulation_time" value="0.11_sec" description="" />
<keyValuePair key="trace_waveform" value="true" description="" />
</section>
</section>
</section>
</webTalkData>

30
lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl → lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl
View File

@@ -1,6 +1,6 @@
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Wed Feb 20 11:22:46 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Wed Feb 27 11:44:18 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
@@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "21" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
@@ -22,21 +22,11 @@ webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key File_Counter -value "3" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "69 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "4 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "45" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "15" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "0.78_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "41208_KB" -context "xsim\\usage"
webtalk_transmit -clientid 1004531601 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "25 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6064_KB" -context "xsim\\usage"
webtalk_transmit -clientid 1469323063 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/xsim.mem Normal file
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BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/xsim.mem
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21
lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/obj/xsim_1.c
View File

@@ -46,15 +46,14 @@ typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_2(char*, char *);
extern void execute_3(char*, char *);
extern void execute_17(char*, char *);
extern void execute_19(char*, char *);
extern void execute_31(char*, char *);
extern void execute_32(char*, char *);
extern void execute_33(char*, char *);
extern void execute_34(char*, char *);
extern void execute_35(char*, char *);
extern void execute_36(char*, char *);
extern void execute_22(char*, char *);
extern void execute_23(char*, char *);
extern void execute_37(char*, char *);
extern void execute_24(char*, char *);
extern void execute_25(char*, char *);
extern void execute_26(char*, char *);
@@ -63,23 +62,23 @@ extern void execute_28(char*, char *);
extern void execute_29(char*, char *);
extern void execute_30(char*, char *);
extern void execute_6(char*, char *);
extern void execute_14(char*, char *);
extern void execute_19(char*, char *);
extern void execute_20(char*, char *);
extern void execute_8(char*, char *);
extern void execute_16(char*, char *);
extern void execute_21(char*, char *);
extern void execute_37(char*, char *);
extern void execute_22(char*, char *);
extern void execute_23(char*, char *);
extern void execute_38(char*, char *);
extern void execute_39(char*, char *);
extern void execute_40(char*, char *);
extern void execute_41(char*, char *);
extern void execute_42(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
extern void transaction_10(char*, char*, unsigned, unsigned, unsigned);
funcp funcTab[30] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_17, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_6, (funcp)execute_14, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_10};
const int NumRelocateId= 30;
funcp funcTab[29] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_19, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_6, (funcp)execute_8, (funcp)execute_16, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 29;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/regFile_tb_behav/xsim.reloc", (void **)funcTab, 30);
iki_relocate(dp, "xsim.dir/regFile_tb_behav/xsim.reloc", (void **)funcTab, 29);
/*Populate the transaction function pointer field in the whole net structure */
}

10
lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml
View File

@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Wed Feb 20 11:30:13 2019'>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Wed Feb 27 11:47:34 2019'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2405991" description="" />
<keyValuePair key="date_generated" value="Wed Feb 20 11:30:12 2019" description="" />
<keyValuePair key="date_generated" value="Wed Feb 27 11:47:33 2019" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
<keyValuePair key="project_iteration" value="6" description="" />
<keyValuePair key="project_iteration" value="10" description="" />
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
<keyValuePair key="route_design" value="FALSE" description="" />
@@ -35,8 +35,8 @@
<section name="usage" level="2" order="2" description="">
<keyValuePair key="iteration" value="0" description="" />
<keyValuePair key="runtime" value="70 ns" description="" />
<keyValuePair key="simulation_memory" value="6120_KB" description="" />
<keyValuePair key="simulation_time" value="0.08_sec" description="" />
<keyValuePair key="simulation_memory" value="6124_KB" description="" />
<keyValuePair key="simulation_time" value="0.12_sec" description="" />
<keyValuePair key="trace_waveform" value="true" description="" />
</section>
</section>

28
lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl
View File

@@ -1,6 +1,6 @@
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Wed Feb 20 11:30:23 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Wed Feb 27 12:02:56 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
@@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "7" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "17" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
@@ -22,21 +22,11 @@ webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key File_Counter -value "3" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "73 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "4 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "37" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "9" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "0.65_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "38732_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3938710361 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "70 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6104_KB" -context "xsim\\usage"
webtalk_transmit -clientid 1751969665 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/xsim.mem
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BIN
lab2CA.sim/sim_1/behav/xsim/xvlog.pb
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80
lab2CA.srcs/sources_1/new/ALU.v
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@@ -63,46 +63,46 @@ module ALU(
endmodule
//testbench
//module alu_tb();
//reg [8:0] a;
//reg [8:0] b;
//reg [2:0] c;
//wire [8:0] d;
module alu_tb();
reg [8:0] a;
reg [8:0] b;
reg [2:0] c;
wire [8:0] d;
//ALU alu0(
//.operand0(a),
//.operand1(b),
//.opcode(c),
//.result(d));
ALU alu0(
.operand0(a),
.operand1(b),
.opcode(c),
.result(d));
// initial begin
// a = 9'b000000111;
// b = 9'b000111000;
// c = 3'b000;
// #5
// a = 9'b000011000;
// b = 9'b000011000;
// c = 3'b001;
// #5
// a = 9'b101010100;
// b = 9'b010101011;
// c = 3'b010;
// #5
// a = 9'b101010100;
// b = 9'b010101000;
// c = 3'b011;
// #5
// a = 9'b000110000;
// b = 9'b000111000;
// c = 3'b100;
// #5
// a = 9'b01011000;
// c = 3'b101;
// #5
// a = 9'b00001010;
// c = 3'b110;
// #5
// #5 $finish;
initial begin
a = 9'b000000111;
b = 9'b000111000;
c = 3'b000;
#5
a = 9'b000011000;
b = 9'b000011000;
c = 3'b001;
#5
a = 9'b101010100;
b = 9'b010101011;
c = 3'b010;
#5
a = 9'b101010100;
b = 9'b010101000;
c = 3'b011;
#5
a = 9'b000110000;
b = 9'b000111000;
c = 3'b100;
#5
a = 9'b01011000;
c = 3'b101;
#5
a = 9'b00001010;
c = 3'b110;
#5
$finish;
// end
//endmodule
end
endmodule

1227
lab2CA.srcs/sources_1/new/BasicModules.v
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File diff suppressed because it is too large Load Diff

105
lab2CA.srcs/sources_1/new/FetchUnit.v
View File

@@ -11,7 +11,7 @@ module FetchUnit(input wire clk, reset,
register PC(
.clk(clk),
.reset(reset),
.En(2'b00),
.En(1'b0),
.Din(result_m),
.Dout(progC_out));
//Adds 1 to the program counter
@@ -31,61 +31,60 @@ module FetchUnit(input wire clk, reset,
endmodule
//testbench
//module fetchUnit_tb();
//reg [8:0] addr_in;
//reg opidx;
//reg reset;
//wire [8:0] addr_out;
module fetchUnit_tb();
reg [8:0] addr_in;
reg opidx,reset,clk;
wire [8:0] addr_out;
// reg clk;
// initial begin
// clk = 1'b0;
// end
// always begin
// #5 clk = ~clk; // Period to be determined
// end
initial begin
clk = 1'b0;
end
always begin
#5 clk = ~clk; // Period to be determined
end
//FetchUnit fetchUnit0(
//.clk(clk),
//.reset(reset),
//.op_idx(opidx),
//.AddrIn(addr_in),
//.AddrOut(addr_out));
FetchUnit tb0(
.clk(clk),
.reset(reset),
.op_idx(opidx),
.AddrIn(addr_in),
.AddrOut(addr_out));
// initial begin
// reset = 0;
// opidx = 1'b1;
// addr_in = 0'b000000000;
// #5
// reset = 1;
// #5
// reset = 0;
// opidx = 1'b0;
// addr_in = 9'b000001111;
// #5
// #5
// addr_in = 9'b011000011;
// #5
// #5
// opidx = 1'b1;
// #5
// #5
// #5
// #5
// opidx = 1'b0;
// addr_in = 9'b000001111;
// #5
// #5
// addr_in = 9'b010010011;
// #5
// opidx = 1'b1;
// #5
// #5
// #5
// #5
// #5 $finish;
initial begin
reset = 0;
opidx = 1'b1;
addr_in = 9'b000000000;
#5
reset = 1;
#5
reset = 0;
opidx = 1'b0;
addr_in = 9'b000001111;
#5
#5
addr_in = 9'b011000011;
#5
#5
opidx = 1'b1;
#5
#5
#5
#5
opidx = 1'b0;
addr_in = 9'b000001111;
#5
#5
addr_in = 9'b010010011;
#5
opidx = 1'b1;
#5
#5
#5
#5
#5
$finish;
// end
//endmodule
end
endmodule

145
lab2CA.srcs/sources_1/new/RegFile.v
View File

@@ -1,39 +1,46 @@
`timescale 1ns / 1ps
module RegFile(input wire clk, reset,
module RegFile(input wire clk, reset, enable,
input wire [1:0] write_index, op0_idx, op1_idx,
input wire [8:0] write_data,
output wire [8:0] op0, op1);
wire [3:0] decOut;
wire [8:0] r0_out, r1_out, r2_out, r3_out;
// To select a register En input must be 2'b00
decoder d0(
.en(enable),
.index(write_index),
.regOut(decOut)
);
register r0(
.clk(clk),
.reset(reset),
.En({write_index[0], write_index[1]}),
.En(decOut[0]),
.Din(write_data),
.Dout(r0_out));
register r1(
.clk(clk),
.reset(reset),
.En({write_index[0], ~write_index[1]}),
.En(decOut[1]),
.Din(write_data),
.Dout(r1_out));
register r2(
.clk(clk),
.reset(reset),
.En({~write_index[0], write_index[1]}),
.En(decOut[2]),
.Din(write_data),
.Dout(r2_out));
register r3(
.clk(clk),
.reset(reset),
.En({~write_index[0], ~write_index[1]}),
.En(decOut[4]),
.Din(write_data),
.Dout(r3_out));
@@ -57,12 +64,11 @@ endmodule
//testbench
module regFile_tb();
reg [8:0] write_d;
reg [1:0] w_idx, op0_idx, op1_idx;
reg reset;
wire [8:0] op0,op1;
reg [8:0] write_d;
reg [1:0] w_idx, op0_idx, op1_idx;
reg reset,clk, enable;
wire [8:0] op0,op1;
reg clk;
initial begin
clk = 1'b0;
end
@@ -70,66 +76,69 @@ wire [8:0] op0,op1;
#5 clk = ~clk; // Period to be determined
end
RegFile regFile0(
.clk(clk),
.reset(reset),
.write_index(w_idx),
.op0_idx(op0_idx),
.op1_idx(op1_idx),
.write_data(write_d),
.op0(op0),
.op1(op1));
RegFile regFile0(
.clk(clk),
.enable(enable),
.reset(reset),
.write_index(w_idx),
.op0_idx(op0_idx),
.op1_idx(op1_idx),
.write_data(write_d),
.op0(op0),
.op1(op1));
initial begin
reset = 0;
#5
reset = 1;
#5
reset = 0;
w_idx = 2'b00;
op0_idx = 2'b00;
op1_idx = 2'b00;
write_d = 9'b000000011;
#5
w_idx = 2'b01;
#5
w_idx = 2'b10;
#5
w_idx = 2'b11;
#5
reset = 0;
w_idx = 2'b00;
op0_idx = 2'b10;
op1_idx = 2'b11;
write_d = 9'b001111000;
#5
reset = 0;
w_idx = 2'b01;
op0_idx = 2'b00;
op1_idx = 2'b01;
write_d = 9'b000001111;
#5
reset = 0;
w_idx = 2'b10;
op0_idx = 2'b00;
op1_idx = 2'b10;
write_d = 9'b111000001;
#5
reset = 0;
w_idx = 2'b11;
op0_idx = 2'b11;
op1_idx = 2'b10;
write_d = 9'b100110001;
#5
reset = 1;
w_idx = 2'b00;
#5
w_idx = 2'b10;
#5
w_idx = 2'b01;
#5
w_idx = 2'b11;
#5 $finish;
reset = 0;
#5
reset = 1;
#5
reset = 0;
enable = 1;
w_idx = 2'b00;
op0_idx = 2'b00;
op1_idx = 2'b00;
write_d = 9'b000000011;
#5
w_idx = 2'b01;
#5
w_idx = 2'b10;
#5
w_idx = 2'b11;
#5
reset = 0;
w_idx = 2'b00;
op0_idx = 2'b10;
op1_idx = 2'b11;
write_d = 9'b001111000;
#5
reset = 0;
w_idx = 2'b01;
op0_idx = 2'b00;
op1_idx = 2'b01;
write_d = 9'b000001111;
#5
reset = 0;
w_idx = 2'b10;
op0_idx = 2'b00;
op1_idx = 2'b10;
write_d = 9'b111000001;
#5
reset = 0;
w_idx = 2'b11;
op0_idx = 2'b11;
op1_idx = 2'b10;
write_d = 9'b100110001;
#5
reset = 1;
w_idx = 2'b00;
#5
w_idx = 2'b10;
#5
w_idx = 2'b01;
#5
w_idx = 2'b11;
#5
$finish;
end
endmodule

9
lab2CA.xpr
View File

@@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="71"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -102,12 +102,19 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/regFile_tb_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="regFile_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/regFile_tb_behav.wcfg"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">