William/WMU-ECE-3570-Lab
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Lots of changes

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Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
This commit is contained in:
goochey
2019-02-27 12:06:17 -05:00
parent 0104b0e689
commit c047c801aa
25 changed files with 428 additions and 69 deletions
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28
lab2CA.runs/impl_1/gen_run.xml
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@@ -1,14 +1,16 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
<File Type="PA-TCL" Name="FetchUnit.tcl"/>
<File Type="BITSTR-BMM" Name="FetchUnit_bd.bmm"/>
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="ROUTE-PWR" Name="FetchUnit_power_routed.rpt"/>
<File Type="PA-TCL" Name="FetchUnit.tcl"/>
<File Type="OPT-DCP" Name="FetchUnit_opt.dcp"/>
<File Type="ROUTE-PWR-SUM" Name="FetchUnit_power_summary_routed.pb"/>
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="OPT-HWDEF" Name="FetchUnit.hwdef"/>
<File Type="BG-BGN" Name="FetchUnit.bgn"/>
<File Type="PWROPT-DCP" Name="FetchUnit_pwropt.dcp"/>
<File Type="PLACE-DCP" Name="FetchUnit_placed.dcp"/>
<File Type="PLACE-PRE-SIMILARITY" Name="FetchUnit_incremental_reuse_pre_placed.rpt"/>
<File Type="BG-BGN" Name="FetchUnit.bgn"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="FetchUnit_postplace_pwropt.dcp"/>
<File Type="BG-BIN" Name="FetchUnit.bin"/>
<File Type="PHYSOPT-DCP" Name="FetchUnit_physopt.dcp"/>
@@ -16,8 +18,11 @@
<File Type="ROUTE-ERROR-DCP" Name="FetchUnit_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="FetchUnit_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="FetchUnit_routed_bb.dcp"/>
<File Type="ROUTE-DRC-RPX" Name="FetchUnit_drc_routed.rpx"/>
<File Type="BITSTR-LTX" Name="FetchUnit.ltx"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="FetchUnit_methodology_drc_routed.rpt"/>
<File Type="BITSTR-MMI" Name="FetchUnit.mmi"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="FetchUnit_methodology_drc_routed.pb"/>
<File Type="BITSTR-SYSDEF" Name="FetchUnit.sysdef"/>
<File Type="ROUTE-TIMING-PB" Name="FetchUnit_timing_summary_routed.pb"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="FetchUnit_postroute_physopt.dcp"/>
@@ -26,8 +31,25 @@
<File Type="BITSTR-RBT" Name="FetchUnit.rbt"/>
<File Type="BITSTR-NKY" Name="FetchUnit.nky"/>
<File Type="BG-DRC" Name="FetchUnit.drc"/>
<File Type="ROUTE-CLK" Name="FetchUnit_clock_utilization_routed.rpt"/>
<File Type="RDI-RDI" Name="FetchUnit.vdi"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<File Type="OPT-DRC" Name="FetchUnit_drc_opted.rpt"/>
<File Type="PLACE-UTIL" Name="FetchUnit_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="FetchUnit_utilization_placed.pb"/>
<File Type="PLACE-IO" Name="FetchUnit_io_placed.rpt"/>
<File Type="PLACE-CTRL" Name="FetchUnit_control_sets_placed.rpt"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="FetchUnit_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-RPX" Name="FetchUnit_timing_summary_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="FetchUnit_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="FetchUnit_route_status.pb"/>
<File Type="ROUTE-PWR-RPX" Name="FetchUnit_power_routed.rpx"/>
<File Type="ROUTE-DRC" Name="FetchUnit_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="FetchUnit_drc_routed.pb"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="FetchUnit_methodology_drc_routed.rpx"/>
<File Type="ROUTE-BUS-SKEW" Name="FetchUnit_bus_skew_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW-RPX" Name="FetchUnit_bus_skew_routed.rpx"/>
<File Type="ROUTE-BUS-SKEW-PB" Name="FetchUnit_bus_skew_routed.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">

2
lab2CA.runs/synth_1/gen_run.xml
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@@ -4,6 +4,8 @@
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="RDS-RDS" Name="FetchUnit.vds"/>
<File Type="RDS-DCP" Name="FetchUnit.dcp"/>
<File Type="RDS-UTIL" Name="FetchUnit_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="FetchUnit_utilization_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">

11
lab2CA.sim/sim_1/behav/xsim/decoder_tb.tcl Normal file
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@@ -0,0 +1,11 @@
set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

9
lab2CA.sim/sim_1/behav/xsim/decoder_tb_vlog.prj Normal file
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@@ -0,0 +1,9 @@
# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort

14
lab2CA.sim/sim_1/behav/xsim/webtalk.jou
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@@ -2,11 +2,11 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Thu Feb 21 15:07:17 2019
# Process ID: 4960
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
# Start of session at: Wed Feb 27 11:47:34 2019
# Process ID: 6784
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/REPOSITORIES/Educational/Western -notrace
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace

4
lab2CA.sim/sim_1/behav/xsim/webtalk_11820.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou
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@@ -2,8 +2,8 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 17:37:48 2019
# Process ID: 11820
# Start of session at: Wed Feb 27 11:43:09 2019
# Process ID: 1408
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log

8
lab2CA.sim/sim_1/behav/xsim/webtalk_11568.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou
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@@ -2,11 +2,11 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Feb 20 10:48:52 2019
# Process ID: 11568
# Start of session at: Wed Feb 27 11:39:16 2019
# Process ID: 14864
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace

8
lab2CA.sim/sim_1/behav/xsim/webtalk_11844.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou
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@@ -2,11 +2,11 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Feb 20 10:53:42 2019
# Process ID: 11844
# Start of session at: Wed Feb 27 11:36:59 2019
# Process ID: 7276
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace

BIN
lab2CA.sim/sim_1/behav/xsim/xelab.pb
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Binary file not shown.

1
lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/Compile_Options.txt Normal file
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@@ -0,0 +1 @@
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "decoder_tb_behav" "xil_defaultlib.decoder_tb" "xil_defaultlib.glbl" -log "elaborate.log"

1
lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/TempBreakPointFile.txt Normal file
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@@ -0,0 +1 @@
Breakpoint File Version 1.0

108
lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/obj/xsim_1.c Normal file
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@@ -0,0 +1,108 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_4(char*, char *);
extern void execute_9(char*, char *);
extern void execute_10(char*, char *);
extern void execute_11(char*, char *);
extern void execute_3(char*, char *);
extern void execute_6(char*, char *);
extern void execute_7(char*, char *);
extern void execute_8(char*, char *);
extern void execute_12(char*, char *);
extern void execute_13(char*, char *);
extern void execute_14(char*, char *);
extern void execute_15(char*, char *);
extern void execute_16(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[14] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 14;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/decoder_tb_behav/xsim.reloc", (void **)funcTab, 14);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/decoder_tb_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/decoder_tb_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/decoder_tb_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/decoder_tb_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/decoder_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

44
lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml Normal file
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@@ -0,0 +1,44 @@
<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Wed Feb 27 11:39:16 2019'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2405991" description="" />
<keyValuePair key="date_generated" value="Wed Feb 27 11:39:15 2019" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
<keyValuePair key="project_iteration" value="2" description="" />
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
<keyValuePair key="route_design" value="FALSE" description="" />
<keyValuePair key="target_device" value="not_applicable" description="" />
<keyValuePair key="target_family" value="not_applicable" description="" />
<keyValuePair key="target_package" value="not_applicable" description="" />
<keyValuePair key="target_speed" value="not_applicable" description="" />
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
</section>
<section name="user_environment" level="1" order="2" description="">
<keyValuePair key="cpu_name" value="Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" description="" />
<keyValuePair key="cpu_speed" value="3492 MHz" description="" />
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
<keyValuePair key="system_ram" value="34.000 GB" description="" />
<keyValuePair key="total_processors" value="1" description="" />
</section>
<section name="vivado_usage" level="1" order="3" description="">
</section>
<section name="xsim" level="1" order="4" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="command" value="xsim" description="" />
</section>
<section name="usage" level="2" order="2" description="">
<keyValuePair key="iteration" value="0" description="" />
<keyValuePair key="runtime" value="30 ns" description="" />
<keyValuePair key="simulation_memory" value="6624_KB" description="" />
<keyValuePair key="simulation_time" value="0.11_sec" description="" />
<keyValuePair key="trace_waveform" value="true" description="" />
</section>
</section>
</section>
</webTalkData>

32
lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl Normal file
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@@ -0,0 +1,32 @@
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Wed Feb 27 11:44:18 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device"
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "25 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6064_KB" -context "xsim\\usage"
webtalk_transmit -clientid 1469323063 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/xsim.mem Normal file
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21
lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/obj/xsim_1.c
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@@ -46,15 +46,14 @@ typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_2(char*, char *);
extern void execute_3(char*, char *);
extern void execute_17(char*, char *);
extern void execute_19(char*, char *);
extern void execute_31(char*, char *);
extern void execute_32(char*, char *);
extern void execute_33(char*, char *);
extern void execute_34(char*, char *);
extern void execute_35(char*, char *);
extern void execute_36(char*, char *);
extern void execute_22(char*, char *);
extern void execute_23(char*, char *);
extern void execute_37(char*, char *);
extern void execute_24(char*, char *);
extern void execute_25(char*, char *);
extern void execute_26(char*, char *);
@@ -63,23 +62,23 @@ extern void execute_28(char*, char *);
extern void execute_29(char*, char *);
extern void execute_30(char*, char *);
extern void execute_6(char*, char *);
extern void execute_14(char*, char *);
extern void execute_19(char*, char *);
extern void execute_20(char*, char *);
extern void execute_8(char*, char *);
extern void execute_16(char*, char *);
extern void execute_21(char*, char *);
extern void execute_37(char*, char *);
extern void execute_22(char*, char *);
extern void execute_23(char*, char *);
extern void execute_38(char*, char *);
extern void execute_39(char*, char *);
extern void execute_40(char*, char *);
extern void execute_41(char*, char *);
extern void execute_42(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
extern void transaction_10(char*, char*, unsigned, unsigned, unsigned);
funcp funcTab[30] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_17, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_6, (funcp)execute_14, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_10};
const int NumRelocateId= 30;
funcp funcTab[29] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_19, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_6, (funcp)execute_8, (funcp)execute_16, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 29;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/regFile_tb_behav/xsim.reloc", (void **)funcTab, 30);
iki_relocate(dp, "xsim.dir/regFile_tb_behav/xsim.reloc", (void **)funcTab, 29);
/*Populate the transaction function pointer field in the whole net structure */
}

10
lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml
View File

@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Wed Feb 20 11:30:13 2019'>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Wed Feb 27 11:47:34 2019'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2405991" description="" />
<keyValuePair key="date_generated" value="Wed Feb 20 11:30:12 2019" description="" />
<keyValuePair key="date_generated" value="Wed Feb 27 11:47:33 2019" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
<keyValuePair key="project_iteration" value="6" description="" />
<keyValuePair key="project_iteration" value="10" description="" />
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
<keyValuePair key="route_design" value="FALSE" description="" />
@@ -35,8 +35,8 @@
<section name="usage" level="2" order="2" description="">
<keyValuePair key="iteration" value="0" description="" />
<keyValuePair key="runtime" value="70 ns" description="" />
<keyValuePair key="simulation_memory" value="6120_KB" description="" />
<keyValuePair key="simulation_time" value="0.08_sec" description="" />
<keyValuePair key="simulation_memory" value="6124_KB" description="" />
<keyValuePair key="simulation_time" value="0.12_sec" description="" />
<keyValuePair key="trace_waveform" value="true" description="" />
</section>
</section>

28
lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl
View File

@@ -1,6 +1,6 @@
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Wed Feb 20 11:30:23 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Wed Feb 27 12:02:56 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
@@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "7" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "17" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
@@ -22,21 +22,11 @@ webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key File_Counter -value "3" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "73 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "4 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "37" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "9" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "0.65_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "38732_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3938710361 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "70 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6104_KB" -context "xsim\\usage"
webtalk_transmit -clientid 1751969665 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/xsim.mem
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lab2CA.sim/sim_1/behav/xsim/xvlog.pb
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52
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -295,6 +295,52 @@ module and9bit_tb();
end
endmodule
module decoder (
input wire en,
input wire [1:0] index,
output reg [3:0] regOut);
always @(en, index)begin
if(en == 1)begin
case(index)
2'b00: regOut <= 4'b0001;
2'b01: regOut <= 4'b0010;
2'b10: regOut <= 4'b0100;
2'b11: regOut <= 4'b1000;
default: regOut <= 4'bxxxx;
endcase
end
end
endmodule
//testbench
module decoder_tb();
reg enable;
reg [1:0] indexIn;
wire [3:0] regOut;
decoder dec0(
.en(enable),
.index(indexIn),
.regOut(regOut));
initial begin
enable = 0;
indexIn = 2'b00;
#5
enable = 1;
#5
indexIn = 2'b01;
#5
indexIn = 2'b10;
#5
indexIn = 2'b11;
#5
$finish;
end
endmodule
module gen_clock();
reg clk;
initial begin
@@ -305,7 +351,7 @@ module gen_clock();
end
endmodule
module mux_2_1 tb0(
module mux_2_1(
input wire switch,
input wire [8:0] A,B,
output reg [8:0] out);
@@ -850,7 +896,7 @@ endmodule
module register(
input wire clk, reset,
input wire [1:0] En,
input wire En,
input wire [8:0] Din,
output reg [8:0] Dout);
@@ -858,7 +904,7 @@ module register(
if (reset == 1'b1) begin
Dout = 9'b000000000;
end
else if (En == 2'b00) begin
else if (En == 1'b0) begin
Dout = Din;
end
else begin

4
lab2CA.srcs/sources_1/new/FetchUnit.v
View File

@@ -11,7 +11,7 @@ module FetchUnit(input wire clk, reset,
register PC(
.clk(clk),
.reset(reset),
.En(2'b00),
.En(1'b0),
.Din(result_m),
.Dout(progC_out));
//Adds 1 to the program counter
@@ -55,7 +55,7 @@ module fetchUnit_tb();
initial begin
reset = 0;
opidx = 1'b1;
addr_in = 0'b000000000;
addr_in = 9'b000000000;
#5
reset = 1;
#5

21
lab2CA.srcs/sources_1/new/RegFile.v
View File

@@ -1,39 +1,46 @@
`timescale 1ns / 1ps
module RegFile(input wire clk, reset,
module RegFile(input wire clk, reset, enable,
input wire [1:0] write_index, op0_idx, op1_idx,
input wire [8:0] write_data,
output wire [8:0] op0, op1);
wire [3:0] decOut;
wire [8:0] r0_out, r1_out, r2_out, r3_out;
// To select a register En input must be 2'b00
decoder d0(
.en(enable),
.index(write_index),
.regOut(decOut)
);
register r0(
.clk(clk),
.reset(reset),
.En({write_index[0], write_index[1]}),
.En(decOut[0]),
.Din(write_data),
.Dout(r0_out));
register r1(
.clk(clk),
.reset(reset),
.En({write_index[0], ~write_index[1]}),
.En(decOut[1]),
.Din(write_data),
.Dout(r1_out));
register r2(
.clk(clk),
.reset(reset),
.En({~write_index[0], write_index[1]}),
.En(decOut[2]),
.Din(write_data),
.Dout(r2_out));
register r3(
.clk(clk),
.reset(reset),
.En({~write_index[0], ~write_index[1]}),
.En(decOut[4]),
.Din(write_data),
.Dout(r3_out));
@@ -59,7 +66,7 @@ endmodule
module regFile_tb();
reg [8:0] write_d;
reg [1:0] w_idx, op0_idx, op1_idx;
reg reset,clk;
reg reset,clk, enable;
wire [8:0] op0,op1;
initial begin
@@ -71,6 +78,7 @@ module regFile_tb();
RegFile regFile0(
.clk(clk),
.enable(enable),
.reset(reset),
.write_index(w_idx),
.op0_idx(op0_idx),
@@ -85,6 +93,7 @@ module regFile_tb();
reset = 1;
#5
reset = 0;
enable = 1;
w_idx = 2'b00;
op0_idx = 2'b00;
op1_idx = 2'b00;

12
lab2CA.xpr
View File

@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="39" Path="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr">
<Project Version="7" Minor="39" Path="C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
@@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="61"/>
<Option Name="WTXSimLaunchSim" Val="71"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -102,13 +102,19 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/regFile_tb_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="fetchUnit_tb"/>
<Option Name="TopModule" Val="regFile_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/regFile_tb_behav.wcfg"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">

79
regFile_tb_behav.wcfg Normal file
View File

@@ -0,0 +1,79 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="regFile_tb_behav.wdb" id="1">
<top_modules>
<top_module name="glbl" />
<top_module name="regFile_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="70000001fs"></ZoomEndTime>
<Cursor1Time time="70000000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="116"></NameColumnWidth>
<ValueColumnWidth column_width="116"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="14" />
<wvobject fp_name="/regFile_tb/write_d" type="array">
<obj_property name="ElementShortName">write_d[8:0]</obj_property>
<obj_property name="ObjectShortName">write_d[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/w_idx" type="array">
<obj_property name="ElementShortName">w_idx[1:0]</obj_property>
<obj_property name="ObjectShortName">w_idx[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/op0_idx" type="array">
<obj_property name="ElementShortName">op0_idx[1:0]</obj_property>
<obj_property name="ObjectShortName">op0_idx[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/op1_idx" type="array">
<obj_property name="ElementShortName">op1_idx[1:0]</obj_property>
<obj_property name="ObjectShortName">op1_idx[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/reset" type="logic">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/enable" type="logic">
<obj_property name="ElementShortName">enable</obj_property>
<obj_property name="ObjectShortName">enable</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/op0" type="array">
<obj_property name="ElementShortName">op0[8:0]</obj_property>
<obj_property name="ObjectShortName">op0[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/op1" type="array">
<obj_property name="ElementShortName">op1[8:0]</obj_property>
<obj_property name="ObjectShortName">op1[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/regFile0/decOut" type="array">
<obj_property name="ElementShortName">decOut[3:0]</obj_property>
<obj_property name="ObjectShortName">decOut[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/regFile0/r0_out" type="array">
<obj_property name="ElementShortName">r0_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r0_out[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/regFile0/r1_out" type="array">
<obj_property name="ElementShortName">r1_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r1_out[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/regFile0/r2_out" type="array">
<obj_property name="ElementShortName">r2_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r2_out[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/regFile0/r3_out" type="array">
<obj_property name="ElementShortName">r3_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r3_out[8:0]</obj_property>
</wvobject>
</wave_config>