Possible mistake

2019-02-25 13:30:58 -05:00
parent 39b9ea781e
commit 0104b0e689
1 changed files with 0 additions and 5 deletions
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -305,11 +305,6 @@ module gen_clock();
    end
 endmodule

-//testbench
-module gen_clock_tb();
-    reg clk;
-   gen
-
 module mux_2_1 tb0(
    input wire switch,
    input wire [8:0] A,B,