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Possible mistake

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WilliamMiceli committed 2019-02-25 13:30:58 -05:00
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commit 0104b0e689
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lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -305,11 +305,6 @@ module gen_clock();
end
endmodule
//testbench
module gen_clock_tb();
reg clk;
gen
module mux_2_1 tb0(
input wire switch,
input wire [8:0] A,B,