c047c801aa
Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
ECE 3570 Lab
Fixes To Be Implemented
- Get rid of the double zero for the enable on the registers
- Make decoder for it
- Redo simulations with other registers using internal signals
- Fix simulation waveforms for Registers, as we are currently changing inputs too quickly (multiple times within a clock cycle)
- Only two registers are being written to, first two within simulation is not being written to
- Need to allow for signed numbers
- Remove subtraction from ALU
- Have arithmetic shift left and right
Uncomment all testbenches(We can have multiple testbenches active at once)- Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only
- Comparator needed
- Make subtraction more efficient
- Need to verify that FetchUnit is working properly as Martin had some concerns that it probably wasn't functioning properly