Created CPU9bits file

2019-03-10 13:42:30 -04:00
parent 8a903ebcfd
commit 172238b4e0
3 changed files with 53 additions and 1 deletions
--- a/lab2CA.srcs/sources_1/new/RegFile.v
+++ b/lab2CA.srcs/sources_1/new/RegFile.v
@@ -16,6 +16,7 @@ module RegFile(input wire clk, reset, enable,
        .regOut(decOut)
    );
    
+    
    register r0(
        .clk(clk),
        .reset(reset),