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Adjusted indentation of testbench code

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This commit is contained in:
WilliamMiceli
2019-02-25 13:27:22 -05:00
parent 7c83a77713
commit 1734d58b47
5 changed files with 680 additions and 690 deletions
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3
README.md
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@@ -10,8 +10,7 @@
* Need to allow for signed numbers * Need to allow for signed numbers
* Remove subtraction from ALU * Remove subtraction from ALU
* Have arithmetic shift left and right * Have arithmetic shift left and right
* <strike>Uncomment all testbenches</strike> * <strike>Uncomment all testbenches</strike> (We can have multiple testbenches active at once)
* We can have multiple testbenches active at once
* Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only * Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only
* Comparator needed * Comparator needed
* Make subtraction more efficient * Make subtraction more efficient

4
lab2CA.srcs/sources_1/new/ALU.v
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@@ -62,7 +62,7 @@ module ALU(
endmodule endmodule
testbench //testbench
module alu_tb(); module alu_tb();
reg [8:0] a; reg [8:0] a;
reg [8:0] b; reg [8:0] b;
@@ -102,7 +102,7 @@ ALU alu0(
a = 9'b00001010; a = 9'b00001010;
c = 3'b110; c = 3'b110;
#5 #5
#5 $finish; $finish;
end end
endmodule endmodule

101
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -20,7 +20,7 @@ reg x;
wire y; wire y;
wire z; wire z;
add_1bit add0( add_1bit tb0(
.A(v), .A(v),
.B(w), .B(w),
.Cin(x), .Cin(x),
@@ -47,6 +47,9 @@ add_1bit add0(
v = 1; v = 1;
w = 1; w = 1;
x = 1; x = 1;
#5
$finish;
end end
endmodule endmodule
@@ -133,13 +136,12 @@ endmodule
//testbench //testbench
module add9bit_tb(); module add9bit_tb();
reg [8:0] a; reg [8:0] a,b;
reg [8:0] b;
reg cin; reg cin;
wire [8:0] s; wire [8:0] s;
wire cout; wire cout;
add_9bit add0( add_9bit tb0(
.A(a), .A(a),
.B(b), .B(b),
.Cin(cin), .Cin(cin),
@@ -181,8 +183,7 @@ endmodule
//testbench //testbench
module and1bit_tb(); module and1bit_tb();
reg a; reg a,b;
reg b;
wire c; wire c;
and_1bit and0( and_1bit and0(
@@ -202,7 +203,8 @@ and_1bit and0(
#5 #5
a = 1; a = 1;
b = 1; b = 1;
#5 $finish; #5
$finish;
end end
endmodule endmodule
@@ -261,8 +263,7 @@ endmodule
//testbench //testbench
module and9bit_tb(); module and9bit_tb();
reg [8:0] a; reg [8:0] a,b;
reg [8:0] b;
wire [8:0] c; wire [8:0] c;
and_9bit and0( and_9bit and0(
@@ -288,7 +289,8 @@ and_9bit and0(
#5 #5
a = 9'b000100001; a = 9'b000100001;
b = 9'b000100001; b = 9'b000100001;
#5 $finish; #5
$finish;
end end
endmodule endmodule
@@ -303,13 +305,13 @@ module gen_clock();
end end
endmodule endmodule
testbench //testbench
module gen_clock_tb(); module gen_clock_tb();
reg clk; reg clk;
gen gen
module mux_2_1(input wire switch, module mux_2_1 tb0(
input wire switch,
input wire [8:0] A,B, input wire [8:0] A,B,
output reg [8:0] out); output reg [8:0] out);
@@ -320,17 +322,15 @@ module mux_2_1(input wire switch,
default : out = 9'bxxxxxxxxx; default : out = 9'bxxxxxxxxx;
endcase endcase
end end
endmodule endmodule
//testbench //testbench
module mux_2_1_tb(); module mux_2_1_tb();
reg s; reg s;
reg [8:0] a; reg [8:0] a,b;
reg [8:0] b;
wire [8:0] c; wire [8:0] c;
mux_2_1 mux0( mux_2_1 tb0(
.switch(s), .switch(s),
.A(a), .A(a),
.B(b), .B(b),
@@ -360,7 +360,8 @@ mux_2_1 mux0(
s = 1; s = 1;
a = 9'b000010001; a = 9'b000010001;
b = 9'b000010111; b = 9'b000010111;
#5 $finish; #5
$finish;
end end
endmodule endmodule
@@ -384,13 +385,10 @@ endmodule
//testbench //testbench
module mux_4_1_tb(); module mux_4_1_tb();
reg [1:0] s; reg [1:0] s;
reg [8:0] a; reg [8:0] a,b,c,d;
reg [8:0] b;
reg [8:0] c;
reg [8:0] d;
wire [8:0] e; wire [8:0] e;
mux_4_1 mux1( mux_4_1 tb0(
.switch(s), .switch(s),
.A(a), .A(a),
.B(b), .B(b),
@@ -422,7 +420,8 @@ mux_4_1 mux1(
b = 9'b000111100; b = 9'b000111100;
c = 9'b001001001; c = 9'b001001001;
d = 9'b100000000; d = 9'b100000000;
#5 $finish; #5
$finish;
end end
endmodule endmodule
@@ -445,23 +444,15 @@ module mux_8_1(
default : out = 9'bxxxxxxxxx; default : out = 9'bxxxxxxxxx;
endcase endcase
end end
endmodule endmodule
//testbench //testbench
module mux_8_1_tb(); module mux_8_1_tb();
reg [2:0] s; reg [2:0] s;
reg [8:0] a; reg [8:0] a,b,c,d,e,f,g,h;
reg [8:0] b;
reg [8:0] c;
reg [8:0] d;
reg [8:0] e;
reg [8:0] f;
reg [8:0] g;
reg [8:0] h;
wire [8:0] out; wire [8:0] out;
mux_8_1 mux1( mux_8_1 tb0(
.switch(s), .switch(s),
.A(a), .A(a),
.B(b), .B(b),
@@ -497,7 +488,8 @@ mux_8_1 mux1(
s = 3'b110; s = 3'b110;
#5 #5
s = 3'b111; s = 3'b111;
#5 $finish; #5
$finish;
end end
endmodule endmodule
@@ -564,7 +556,8 @@ nor_1bit nor0(
#5 #5
a = 1; a = 1;
b = 1; b = 1;
#5 $finish; #5
$finish;
end end
endmodule endmodule
@@ -650,7 +643,8 @@ nor_9bit nor0(
#5 #5
a = 9'b000100001; a = 9'b000100001;
b = 9'b000100001; b = 9'b000100001;
#5 $finish; #5
$finish;
end end
endmodule endmodule
@@ -677,7 +671,8 @@ not_1bit not0(
a = 0; a = 0;
#5 #5
a = 1; a = 1;
#5 $finish; #5
$finish;
end end
endmodule endmodule
@@ -747,10 +742,10 @@ wire [8:0] b;
a = 9'b111111111; a = 9'b111111111;
#5 #5
a = 9'b100000001; a = 9'b100000001;
#5 $finish; #5
$finish;
end end
endmodule endmodule
module or_1bit( module or_1bit(
@@ -785,10 +780,10 @@ wire c;
#5 #5
a = 1; a = 1;
b = 1; b = 1;
#5 $finish; #5
$finish;
end end
endmodule endmodule
module or_9bit( module or_9bit(
@@ -881,13 +876,14 @@ wire [8:0] c;
#5 #5
a = 9'b000000000; a = 9'b000000000;
b = 9'b000010000; b = 9'b000010000;
#5 $finish; #5
$finish;
end end
endmodule endmodule
module register(input wire clk, reset, module register(
input wire clk, reset,
input wire [1:0] En, input wire [1:0] En,
input wire [8:0] Din, input wire [8:0] Din,
output reg [8:0] Dout); output reg [8:0] Dout);
@@ -903,7 +899,6 @@ module register(input wire clk, reset,
Dout = Dout; Dout = Dout;
end end
end end
endmodule endmodule
//testbench //testbench
@@ -957,10 +952,10 @@ wire [8:0] Dout;
clk = 1; clk = 1;
#5 #5
clk = 0; clk = 0;
#5 $finish; #5
$finish;
end end
endmodule endmodule
module shift_logical_left( module shift_logical_left(
@@ -994,10 +989,10 @@ wire [8:0] b;
a = 9'b111111111; a = 9'b111111111;
#5 #5
a = 9'b100000001; a = 9'b100000001;
#5 $finish; #5
$finish;
end end
endmodule endmodule
module shift_logical_right( module shift_logical_right(
@@ -1031,10 +1026,10 @@ wire [8:0] b;
a = 9'b111111111; a = 9'b111111111;
#5 #5
a = 9'b100000001; a = 9'b100000001;
#5 $finish; #5
$finish;
end end
endmodule endmodule
module sub_9bit( module sub_9bit(
@@ -1098,7 +1093,6 @@ wire [8:0] c;
$finish; $finish;
end end
endmodule endmodule
module twos_compliment_9bit( module twos_compliment_9bit(
@@ -1146,5 +1140,4 @@ wire [8:0] b;
$finish; $finish;
end end
endmodule endmodule

6
lab2CA.srcs/sources_1/new/FetchUnit.v
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@@ -33,11 +33,9 @@ endmodule
//testbench //testbench
module fetchUnit_tb(); module fetchUnit_tb();
reg [8:0] addr_in; reg [8:0] addr_in;
reg opidx; reg opidx,reset,clk;
reg reset;
wire [8:0] addr_out; wire [8:0] addr_out;
reg clk;
initial begin initial begin
clk = 1'b0; clk = 1'b0;
end end
@@ -45,7 +43,7 @@ wire [8:0] addr_out;
#5 clk = ~clk; // Period to be determined #5 clk = ~clk; // Period to be determined
end end
FetchUnit fetchUnit0( FetchUnit tb0(
.clk(clk), .clk(clk),
.reset(reset), .reset(reset),
.op_idx(opidx), .op_idx(opidx),

6
lab2CA.srcs/sources_1/new/RegFile.v
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@@ -59,10 +59,9 @@ endmodule
module regFile_tb(); module regFile_tb();
reg [8:0] write_d; reg [8:0] write_d;
reg [1:0] w_idx, op0_idx, op1_idx; reg [1:0] w_idx, op0_idx, op1_idx;
reg reset; reg reset,clk;
wire [8:0] op0,op1; wire [8:0] op0,op1;
reg clk;
initial begin initial begin
clk = 1'b0; clk = 1'b0;
end end
@@ -129,7 +128,8 @@ RegFile regFile0(
w_idx = 2'b01; w_idx = 2'b01;
#5 #5
w_idx = 2'b11; w_idx = 2'b11;
#5 $finish; #5
$finish;
end end
endmodule endmodule