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Adjusted indentation of testbench code

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This commit is contained in:
WilliamMiceli
2019-02-25 13:27:22 -05:00
parent 7c83a77713
commit 1734d58b47
5 changed files with 680 additions and 690 deletions
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3
README.md
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@@ -10,8 +10,7 @@
* Need to allow for signed numbers * Need to allow for signed numbers
* Remove subtraction from ALU * Remove subtraction from ALU
* Have arithmetic shift left and right * Have arithmetic shift left and right
* <strike>Uncomment all testbenches</strike> * <strike>Uncomment all testbenches</strike> (We can have multiple testbenches active at once)
* We can have multiple testbenches active at once
* Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only * Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only
* Comparator needed * Comparator needed
* Make subtraction more efficient * Make subtraction more efficient

78
lab2CA.srcs/sources_1/new/ALU.v
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@@ -62,47 +62,47 @@ module ALU(
endmodule endmodule
testbench //testbench
module alu_tb(); module alu_tb();
reg [8:0] a; reg [8:0] a;
reg [8:0] b; reg [8:0] b;
reg [2:0] c; reg [2:0] c;
wire [8:0] d; wire [8:0] d;
ALU alu0( ALU alu0(
.operand0(a), .operand0(a),
.operand1(b), .operand1(b),
.opcode(c), .opcode(c),
.result(d)); .result(d));
initial begin initial begin
a = 9'b000000111; a = 9'b000000111;
b = 9'b000111000; b = 9'b000111000;
c = 3'b000; c = 3'b000;
#5 #5
a = 9'b000011000; a = 9'b000011000;
b = 9'b000011000; b = 9'b000011000;
c = 3'b001; c = 3'b001;
#5 #5
a = 9'b101010100; a = 9'b101010100;
b = 9'b010101011; b = 9'b010101011;
c = 3'b010; c = 3'b010;
#5 #5
a = 9'b101010100; a = 9'b101010100;
b = 9'b010101000; b = 9'b010101000;
c = 3'b011; c = 3'b011;
#5 #5
a = 9'b000110000; a = 9'b000110000;
b = 9'b000111000; b = 9'b000111000;
c = 3'b100; c = 3'b100;
#5 #5
a = 9'b01011000; a = 9'b01011000;
c = 3'b101; c = 3'b101;
#5 #5
a = 9'b00001010; a = 9'b00001010;
c = 3'b110; c = 3'b110;
#5 #5
#5 $finish; $finish;
end end
endmodule endmodule

1079
lab2CA.srcs/sources_1/new/BasicModules.v
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File diff suppressed because it is too large Load Diff

84
lab2CA.srcs/sources_1/new/FetchUnit.v
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@@ -32,12 +32,10 @@ endmodule
//testbench //testbench
module fetchUnit_tb(); module fetchUnit_tb();
reg [8:0] addr_in; reg [8:0] addr_in;
reg opidx; reg opidx,reset,clk;
reg reset; wire [8:0] addr_out;
wire [8:0] addr_out;
reg clk;
initial begin initial begin
clk = 1'b0; clk = 1'b0;
end end
@@ -45,48 +43,48 @@ wire [8:0] addr_out;
#5 clk = ~clk; // Period to be determined #5 clk = ~clk; // Period to be determined
end end
FetchUnit fetchUnit0( FetchUnit tb0(
.clk(clk), .clk(clk),
.reset(reset), .reset(reset),
.op_idx(opidx), .op_idx(opidx),
.AddrIn(addr_in), .AddrIn(addr_in),
.AddrOut(addr_out)); .AddrOut(addr_out));
initial begin initial begin
reset = 0; reset = 0;
opidx = 1'b1; opidx = 1'b1;
addr_in = 0'b000000000; addr_in = 0'b000000000;
#5 #5
reset = 1; reset = 1;
#5 #5
reset = 0; reset = 0;
opidx = 1'b0; opidx = 1'b0;
addr_in = 9'b000001111; addr_in = 9'b000001111;
#5 #5
#5 #5
addr_in = 9'b011000011; addr_in = 9'b011000011;
#5 #5
#5 #5
opidx = 1'b1; opidx = 1'b1;
#5 #5
#5 #5
#5 #5
#5 #5
opidx = 1'b0; opidx = 1'b0;
addr_in = 9'b000001111; addr_in = 9'b000001111;
#5 #5
#5 #5
addr_in = 9'b010010011; addr_in = 9'b010010011;
#5 #5
opidx = 1'b1; opidx = 1'b1;
#5 #5
#5 #5
#5 #5
#5 #5
#5 #5
$finish; $finish;
end end
endmodule endmodule

126
lab2CA.srcs/sources_1/new/RegFile.v
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@@ -57,12 +57,11 @@ endmodule
//testbench //testbench
module regFile_tb(); module regFile_tb();
reg [8:0] write_d; reg [8:0] write_d;
reg [1:0] w_idx, op0_idx, op1_idx; reg [1:0] w_idx, op0_idx, op1_idx;
reg reset; reg reset,clk;
wire [8:0] op0,op1; wire [8:0] op0,op1;
reg clk;
initial begin initial begin
clk = 1'b0; clk = 1'b0;
end end
@@ -70,66 +69,67 @@ wire [8:0] op0,op1;
#5 clk = ~clk; // Period to be determined #5 clk = ~clk; // Period to be determined
end end
RegFile regFile0( RegFile regFile0(
.clk(clk), .clk(clk),
.reset(reset), .reset(reset),
.write_index(w_idx), .write_index(w_idx),
.op0_idx(op0_idx), .op0_idx(op0_idx),
.op1_idx(op1_idx), .op1_idx(op1_idx),
.write_data(write_d), .write_data(write_d),
.op0(op0), .op0(op0),
.op1(op1)); .op1(op1));
initial begin initial begin
reset = 0; reset = 0;
#5 #5
reset = 1; reset = 1;
#5 #5
reset = 0; reset = 0;
w_idx = 2'b00; w_idx = 2'b00;
op0_idx = 2'b00; op0_idx = 2'b00;
op1_idx = 2'b00; op1_idx = 2'b00;
write_d = 9'b000000011; write_d = 9'b000000011;
#5 #5
w_idx = 2'b01; w_idx = 2'b01;
#5 #5
w_idx = 2'b10; w_idx = 2'b10;
#5 #5
w_idx = 2'b11; w_idx = 2'b11;
#5 #5
reset = 0; reset = 0;
w_idx = 2'b00; w_idx = 2'b00;
op0_idx = 2'b10; op0_idx = 2'b10;
op1_idx = 2'b11; op1_idx = 2'b11;
write_d = 9'b001111000; write_d = 9'b001111000;
#5 #5
reset = 0; reset = 0;
w_idx = 2'b01; w_idx = 2'b01;
op0_idx = 2'b00; op0_idx = 2'b00;
op1_idx = 2'b01; op1_idx = 2'b01;
write_d = 9'b000001111; write_d = 9'b000001111;
#5 #5
reset = 0; reset = 0;
w_idx = 2'b10; w_idx = 2'b10;
op0_idx = 2'b00; op0_idx = 2'b00;
op1_idx = 2'b10; op1_idx = 2'b10;
write_d = 9'b111000001; write_d = 9'b111000001;
#5 #5
reset = 0; reset = 0;
w_idx = 2'b11; w_idx = 2'b11;
op0_idx = 2'b11; op0_idx = 2'b11;
op1_idx = 2'b10; op1_idx = 2'b10;
write_d = 9'b100110001; write_d = 9'b100110001;
#5 #5
reset = 1; reset = 1;
w_idx = 2'b00; w_idx = 2'b00;
#5 #5
w_idx = 2'b10; w_idx = 2'b10;
#5 #5
w_idx = 2'b01; w_idx = 2'b01;
#5 #5
w_idx = 2'b11; w_idx = 2'b11;
#5 $finish; #5
$finish;
end end
endmodule endmodule