Adjusted indentation of testbench code

2019-02-25 13:27:22 -05:00
parent 7c83a77713
commit 1734d58b47
5 changed files with 680 additions and 690 deletions
--- a/README.md
+++ b/README.md
@@ -10,8 +10,7 @@
 * Need to allow for signed numbers
 * Remove subtraction from ALU
 * Have arithmetic shift left and right
-* <strike>Uncomment all testbenches</strike>
-  * We can have multiple testbenches active at once
+* <strike>Uncomment all testbenches</strike> (We can have multiple testbenches active at once)
 * Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only
 * Comparator needed
 * Make subtraction more efficient
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -62,18 +62,18 @@ module ALU(

 endmodule

-testbench
+//testbench
 module alu_tb();
-reg [8:0] a;
-reg [8:0] b;
-reg [2:0] c;
-wire [8:0] d;
+    reg [8:0] a;
+    reg [8:0] b;
+    reg [2:0] c;
+    wire [8:0] d;

-ALU alu0(
-.operand0(a),
-.operand1(b),
-.opcode(c),
-.result(d));
+    ALU alu0(
+        .operand0(a),
+        .operand1(b),
+        .opcode(c),
+        .result(d));
    
    initial begin
        a = 9'b000000111;
@@ -102,7 +102,7 @@ ALU alu0(
        a = 9'b00001010;
        c = 3'b110;
        #5
-   #5 $finish;
+        $finish;

    end
 endmodule
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -14,13 +14,13 @@ endmodule

 //testbench
 module add1bit_tb();
-reg v;
-reg w;
-reg x;
-wire y;
-wire z;
+    reg v;
+    reg w;
+    reg x;
+    wire y;
+    wire z;

-add_1bit add0(
+    add_1bit tb0(
        .A(v),
        .B(w),
        .Cin(x),
@@ -47,6 +47,9 @@ add_1bit add0(
        v = 1;
        w = 1;
        x = 1;
+        #5
+        $finish;
+
    end
 endmodule

@@ -133,13 +136,12 @@ endmodule

 //testbench
 module add9bit_tb();
-reg [8:0] a;
-reg [8:0] b;
-reg cin;
-wire [8:0] s;
-wire cout;
+    reg [8:0] a,b;
+    reg cin;
+    wire [8:0] s;
+    wire cout;

-add_9bit add0(
+    add_9bit tb0(
        .A(a),
        .B(b),
        .Cin(cin),
@@ -181,14 +183,13 @@ endmodule

 //testbench
 module and1bit_tb();
-reg a;
-reg b;
-wire c;
+    reg a,b;
+    wire c;

-and_1bit and0(
-.A(a),
-.B(b),
-.C(c));
+    and_1bit and0(
+        .A(a),
+        .B(b),
+        .C(c));
    
    initial begin
        a = 0;
@@ -202,7 +203,8 @@ and_1bit and0(
        #5
        a = 1;
        b = 1;
-   #5 $finish;
+        #5
+        $finish;

    end
 endmodule
@@ -261,14 +263,13 @@ endmodule

 //testbench
 module and9bit_tb();
-reg [8:0] a;
-reg [8:0] b;
-wire [8:0] c;
+    reg [8:0] a,b;
+    wire [8:0] c;

-and_9bit and0(
-.A(a),
-.B(b),
-.C(c));
+    and_9bit and0(
+        .A(a),
+        .B(b),
+        .C(c));
    
    initial begin
        a = 9'b000000000;
@@ -288,7 +289,8 @@ and_9bit and0(
        #5
        a = 9'b000100001;
        b = 9'b000100001;
-   #5 $finish;
+        #5
+        $finish;

    end
 endmodule
@@ -303,13 +305,13 @@ module gen_clock();
    end
 endmodule

-testbench
+//testbench
 module gen_clock_tb();
-
-reg clk;
+    reg clk;
   gen

-module mux_2_1(input wire switch,
+module mux_2_1 tb0(
+    input wire switch,
    input wire [8:0] A,B,
    output reg [8:0] out);
           
@@ -320,21 +322,19 @@ module mux_2_1(input wire switch,
            default : out = 9'bxxxxxxxxx;
        endcase
    end
-
 endmodule

 //testbench
 module mux_2_1_tb();
-reg s;
-reg [8:0] a;
-reg [8:0] b;
-wire [8:0] c;
+    reg s;
+    reg [8:0] a,b;
+    wire [8:0] c;

-mux_2_1 mux0(
-.switch(s),
-.A(a),
-.B(b),
-.out(c));
+    mux_2_1 tb0(
+        .switch(s),
+        .A(a),
+        .B(b),
+        .out(c));
    
    initial begin
        s = 0;
@@ -360,7 +360,8 @@ mux_2_1 mux0(
        s = 1;
        a = 9'b000010001;
        b = 9'b000010111;
-   #5 $finish;
+        #5
+        $finish;

    end
 endmodule
@@ -383,20 +384,17 @@ endmodule

 //testbench
 module mux_4_1_tb();
-reg [1:0] s;
-reg [8:0] a;
-reg [8:0] b;
-reg [8:0] c;
-reg [8:0] d;
-wire [8:0] e;
+    reg [1:0] s;
+    reg [8:0] a,b,c,d;
+    wire [8:0] e;

-mux_4_1 mux1(
-.switch(s),
-.A(a),
-.B(b),
-.C(c),
-.D(d),
-.out(e));
+    mux_4_1 tb0(
+        .switch(s),
+        .A(a),
+        .B(b),
+        .C(c),
+        .D(d),
+        .out(e));
    
    initial begin
        s = 2'b00;
@@ -422,7 +420,8 @@ mux_4_1 mux1(
        b = 9'b000111100;
        c = 9'b001001001;
        d = 9'b100000000;
-   #5 $finish;
+        #5
+        $finish;

    end
 endmodule
@@ -445,33 +444,25 @@ module mux_8_1(
            default : out = 9'bxxxxxxxxx;
        endcase
    end
-
 endmodule

 //testbench
 module mux_8_1_tb();
-reg [2:0] s;
-reg [8:0] a;
-reg [8:0] b;
-reg [8:0] c;
-reg [8:0] d;
-reg [8:0] e;
-reg [8:0] f;
-reg [8:0] g;
-reg [8:0] h;
-wire [8:0] out;
+    reg [2:0] s;
+    reg [8:0] a,b,c,d,e,f,g,h;
+    wire [8:0] out;

-mux_8_1 mux1(
-.switch(s),
-.A(a),
-.B(b),
-.C(c),
-.D(d),
-.E(e),
-.F(f),
-.G(g),
-.H(h),
-.out(out));
+    mux_8_1 tb0(
+        .switch(s),
+        .A(a),
+        .B(b),
+        .C(c),
+        .D(d),
+        .E(e),
+        .F(f),
+        .G(g),
+        .H(h),
+        .out(out));
    
    initial begin
        s = 3'b000;
@@ -497,7 +488,8 @@ mux_8_1 mux1(
        s = 3'b110;
        #5
        s = 3'b111;
-   #5 $finish;
+        #5
+        $finish;

    end
 endmodule
@@ -543,14 +535,14 @@ endmodule

 //testbench
 module nor_1bit_tb();
-reg a;
-reg b;
-wire c;
+    reg a;
+    reg b;
+    wire c;

-nor_1bit nor0(
-.A(a),
-.B(b),
-.C(c));
+    nor_1bit nor0(
+        .A(a),
+        .B(b),
+        .C(c));
    
    initial begin
        a = 0;
@@ -564,7 +556,8 @@ nor_1bit nor0(
        #5
        a = 1;
        b = 1;
-   #5 $finish;
+        #5
+        $finish;

    end
 endmodule
@@ -623,14 +616,14 @@ endmodule

 //testbench
 module nor_9bit_tb();
-reg [8:0] a;
-reg [8:0] b;
-wire [8:0] c;
+    reg [8:0] a;
+    reg [8:0] b;
+    wire [8:0] c;

-nor_9bit nor0(
-.A(a),
-.B(b),
-.C(c));
+    nor_9bit nor0(
+        .A(a),
+        .B(b),
+        .C(c));
    
    initial begin
        a = 9'b000000000;
@@ -650,7 +643,8 @@ nor_9bit nor0(
        #5
        a = 9'b000100001;
        b = 9'b000100001;
-   #5 $finish;
+        #5
+        $finish;

    end
 endmodule
@@ -666,18 +660,19 @@ endmodule

 //testbench
 module not_1bit_tb();
-reg a;
-wire b;
+    reg a;
+    wire b;

-not_1bit not0(
-.A(a),
-.B(b));
+    not_1bit not0(
+        .A(a),
+        .B(b));
        
    initial begin
        a = 0;
        #5
        a = 1;
-   #5 $finish;
+        #5
+        $finish;

    end
 endmodule
@@ -726,8 +721,8 @@ endmodule

 //testbench
 module not_9bit_tb();
-reg [8:0] a;
-wire [8:0] b;
+    reg [8:0] a;
+    wire [8:0] b;

    not_9bit not0(
        .A(a),
@@ -747,10 +742,10 @@ wire [8:0] b;
        a = 9'b111111111;
        #5
        a = 9'b100000001;
-   #5 $finish;
+        #5
+        $finish;

    end
-
 endmodule

 module or_1bit(
@@ -764,9 +759,9 @@ endmodule

 //testbench
 module or_1bit_tb();
-reg a;
-reg b;
-wire c;
+    reg a;
+    reg b;
+    wire c;

    or_1bit or0(
        .A(a),
@@ -785,10 +780,10 @@ wire c;
        #5
        a = 1;
        b = 1;
-   #5 $finish;
+        #5
+        $finish;

    end
-
 endmodule

 module or_9bit(
@@ -845,9 +840,9 @@ endmodule

 //testbench
 module or_9bit_tb();
-reg [8:0] a;
-reg [8:0] b;
-wire [8:0] c;
+    reg [8:0] a;
+    reg [8:0] b;
+    wire [8:0] c;

    or_9bit tb0(
        .A(a),
@@ -881,13 +876,14 @@ wire [8:0] c;
        #5
        a = 9'b000000000;
        b = 9'b000010000;
-   #5 $finish;
+        #5
+        $finish;

    end
-
 endmodule

-module register(input wire clk, reset,
+module register(
+    input wire clk, reset,
    input wire [1:0] En,
    input wire [8:0] Din,
    output reg [8:0] Dout);
@@ -903,15 +899,14 @@ module register(input wire clk, reset,
        Dout = Dout;
        end
    end
-
 endmodule

 //testbench
 module register_tb();
-reg clk,reset;
-reg [1:0] En;
-reg [8:0] Din;
-wire [8:0] Dout;
+    reg clk,reset;
+    reg [1:0] En;
+    reg [8:0] Din;
+    wire [8:0] Dout;

    register tb0(
        .clk(clk),
@@ -957,10 +952,10 @@ wire [8:0] Dout;
        clk = 1;
        #5
        clk = 0;
-   #5 $finish;
+        #5
+        $finish;

    end
-
 endmodule 
    
 module shift_logical_left(
@@ -973,8 +968,8 @@ endmodule

 //testbench
 module shift_logical_left_tb();
-reg [8:0] a;
-wire [8:0] b;
+    reg [8:0] a;
+    wire [8:0] b;

    shift_logical_left tb0(
        .A(a),
@@ -994,10 +989,10 @@ wire [8:0] b;
        a = 9'b111111111;
        #5
        a = 9'b100000001;
-   #5 $finish;
+        #5
+        $finish;

    end
-
 endmodule

 module shift_logical_right(
@@ -1010,8 +1005,8 @@ endmodule

 //testbench
 module shift_logical_right_tb();
-reg [8:0] a;
-wire [8:0] b;
+    reg [8:0] a;
+    wire [8:0] b;

    shift_logical_right tb0(
        .A(a),
@@ -1031,10 +1026,10 @@ wire [8:0] b;
        a = 9'b111111111;
        #5
        a = 9'b100000001;
-   #5 $finish;
+        #5
+        $finish;

    end
-
 endmodule

 module sub_9bit(
@@ -1058,9 +1053,9 @@ endmodule

 //testbench
 module sub_9bit_tb();
-reg [8:0] a;
-reg [8:0] b;
-wire [8:0] c;
+    reg [8:0] a;
+    reg [8:0] b;
+    wire [8:0] c;

    sub_9bit tb0(
        .A(a),
@@ -1098,7 +1093,6 @@ wire [8:0] c;
        $finish;

    end
-
 endmodule

 module twos_compliment_9bit(
@@ -1121,8 +1115,8 @@ endmodule

 //testbench
 module twos_compliment_tb();
-reg [8:0] a;
-wire [8:0] b;
+    reg [8:0] a;
+    wire [8:0] b;

    twos_compliment_9bit tb0(
        .A(a),
@@ -1146,5 +1140,4 @@ wire [8:0] b;
        $finish;

    end
-
 endmodule
--- a/lab2CA.srcs/sources_1/new/FetchUnit.v
+++ b/lab2CA.srcs/sources_1/new/FetchUnit.v
@@ -32,12 +32,10 @@ endmodule

 //testbench
 module fetchUnit_tb();
-reg [8:0] addr_in;
-reg opidx;
-reg reset;
-wire [8:0] addr_out;
+    reg [8:0] addr_in;
+    reg opidx,reset,clk;
+    wire [8:0] addr_out;

-    reg clk;
    initial begin
        clk = 1'b0;
    end
@@ -45,12 +43,12 @@ wire [8:0] addr_out;
        #5 clk = ~clk; // Period to be determined
    end

-FetchUnit fetchUnit0(
-.clk(clk),
-.reset(reset),
-.op_idx(opidx),
-.AddrIn(addr_in),
-.AddrOut(addr_out));
+    FetchUnit tb0(
+        .clk(clk),
+        .reset(reset),
+        .op_idx(opidx),
+        .AddrIn(addr_in),
+        .AddrOut(addr_out));


    
--- a/lab2CA.srcs/sources_1/new/RegFile.v
+++ b/lab2CA.srcs/sources_1/new/RegFile.v
@@ -57,12 +57,11 @@ endmodule

 //testbench
 module regFile_tb();
-reg [8:0] write_d;
-reg [1:0] w_idx, op0_idx, op1_idx;
-reg reset;
-wire [8:0] op0,op1;
+    reg [8:0] write_d;
+    reg [1:0] w_idx, op0_idx, op1_idx;
+    reg reset,clk;
+    wire [8:0] op0,op1;

-    reg clk;
    initial begin
        clk = 1'b0;
    end
@@ -70,15 +69,15 @@ wire [8:0] op0,op1;
        #5 clk = ~clk; // Period to be determined
    end

-RegFile regFile0(
-.clk(clk),
-.reset(reset),
-.write_index(w_idx),
-.op0_idx(op0_idx),
-.op1_idx(op1_idx),
-.write_data(write_d),
-.op0(op0),
-.op1(op1));
+    RegFile regFile0(
+        .clk(clk),
+        .reset(reset),
+        .write_index(w_idx),
+        .op0_idx(op0_idx),
+        .op1_idx(op1_idx),
+        .write_data(write_d),
+        .op0(op0),
+        .op1(op1));
    
    initial begin
        reset = 0;
@@ -129,7 +128,8 @@ RegFile regFile0(
        w_idx = 2'b01;
        #5
        w_idx = 2'b11;
-    #5 $finish;
+        #5
+        $finish;

    end
 endmodule