Little stuff
This commit is contained in:
@@ -11,15 +11,15 @@
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</db_ref>
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</db_ref>
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</db_ref_list>
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</db_ref_list>
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<zoom_setting>
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<zoom_setting>
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<ZoomStartTime time="65000000fs"></ZoomStartTime>
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<ZoomStartTime time="184634100fs"></ZoomStartTime>
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||||||
<ZoomEndTime time="263400001fs"></ZoomEndTime>
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<ZoomEndTime time="258334101fs"></ZoomEndTime>
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||||||
<Cursor1Time time="107600000fs"></Cursor1Time>
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<Cursor1Time time="315000000fs"></Cursor1Time>
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</zoom_setting>
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</zoom_setting>
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<column_width_setting>
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<column_width_setting>
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<NameColumnWidth column_width="174"></NameColumnWidth>
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<NameColumnWidth column_width="174"></NameColumnWidth>
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<ValueColumnWidth column_width="68"></ValueColumnWidth>
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<ValueColumnWidth column_width="64"></ValueColumnWidth>
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</column_width_setting>
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</column_width_setting>
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<WVObjectSize size="13" />
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<WVObjectSize size="16" />
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<wvobject fp_name="group436" type="group">
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<wvobject fp_name="group436" type="group">
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<obj_property name="label">Program Counter</obj_property>
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<obj_property name="label">Program Counter</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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@@ -49,7 +49,6 @@
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<wvobject fp_name="group191" type="group">
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<wvobject fp_name="group191" type="group">
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<obj_property name="label">Fetch Unit</obj_property>
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<obj_property name="label">Fetch Unit</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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<obj_property name="isExpanded"></obj_property>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FD/FetchU/op_idx" type="logic">
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FD/FetchU/op_idx" type="logic">
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<obj_property name="ElementShortName">op_idx</obj_property>
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<obj_property name="ElementShortName">op_idx</obj_property>
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<obj_property name="ObjectShortName">op_idx</obj_property>
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<obj_property name="ObjectShortName">op_idx</obj_property>
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@@ -248,6 +247,253 @@
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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</wvobject>
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</wvobject>
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</wvobject>
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<wvobject fp_name="group120" type="group">
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<obj_property name="label">ALU</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/opcode" type="array">
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<obj_property name="ElementShortName">opcode[3:0]</obj_property>
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<obj_property name="ObjectShortName">opcode[3:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/operand0" type="array">
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<obj_property name="ElementShortName">operand0[8:0]</obj_property>
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<obj_property name="ObjectShortName">operand0[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/operand1" type="array">
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<obj_property name="ElementShortName">operand1[8:0]</obj_property>
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<obj_property name="ObjectShortName">operand1[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result" type="array">
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<obj_property name="ElementShortName">result[8:0]</obj_property>
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<obj_property name="ObjectShortName">result[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_A" type="array">
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<obj_property name="ElementShortName">result_A[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_A[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_B" type="array">
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<obj_property name="ElementShortName">result_B[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_B[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_C" type="array">
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<obj_property name="ElementShortName">result_C[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_C[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_D" type="array">
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<obj_property name="ElementShortName">result_D[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_D[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_E" type="array">
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<obj_property name="ElementShortName">result_E[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_E[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_F" type="array">
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<obj_property name="ElementShortName">result_F[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_F[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_G" type="array">
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<obj_property name="ElementShortName">result_G[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_G[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_H" type="array">
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<obj_property name="ElementShortName">result_H[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_H[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_I" type="array">
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<obj_property name="ElementShortName">result_I[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_I[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_J" type="array">
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<obj_property name="ElementShortName">result_J[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_J[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_K" type="array">
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<obj_property name="ElementShortName">result_K[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_K[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_L" type="array">
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<obj_property name="ElementShortName">result_L[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_L[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_M" type="array">
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<obj_property name="ElementShortName">result_M[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_M[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_N" type="array">
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<obj_property name="ElementShortName">result_N[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_N[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_O" type="array">
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<obj_property name="ElementShortName">result_O[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_O[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/result_P" type="array">
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<obj_property name="ElementShortName">result_P[8:0]</obj_property>
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<obj_property name="ObjectShortName">result_P[8:0]</obj_property>
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<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/alu/cout" type="logic">
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<obj_property name="ElementShortName">cout</obj_property>
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<obj_property name="ObjectShortName">cout</obj_property>
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</wvobject>
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</wvobject>
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<wvobject fp_name="group308" type="group">
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<obj_property name="label">EM Module</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/reset" type="logic">
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<obj_property name="ElementShortName">reset</obj_property>
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<obj_property name="ObjectShortName">reset</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/clk" type="logic">
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<obj_property name="ElementShortName">clk</obj_property>
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<obj_property name="ObjectShortName">clk</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/PipIn" type="array">
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<obj_property name="ElementShortName">PipIn[50:0]</obj_property>
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<obj_property name="ObjectShortName">PipIn[50:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/PipOut" type="array">
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||||||
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<obj_property name="ElementShortName">PipOut[61:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">PipOut[61:0]</obj_property>
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/instr" type="array">
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||||||
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<obj_property name="ElementShortName">instr[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">instr[8:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/op1" type="array">
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<obj_property name="ElementShortName">op1[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">op1[8:0]</obj_property>
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/op0" type="array">
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||||||
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<obj_property name="ElementShortName">op0[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">op0[8:0]</obj_property>
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/FUAddr" type="array">
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||||||
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<obj_property name="ElementShortName">FUAddr[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">FUAddr[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/FUJB" type="array">
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||||||
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<obj_property name="ElementShortName">FUJB[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">FUJB[8:0]</obj_property>
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/PCout" type="array">
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||||||
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<obj_property name="ElementShortName">PCout[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">PCout[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/JBRes" type="array">
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||||||
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<obj_property name="ElementShortName">JBRes[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">JBRes[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/FUJ" type="array">
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||||||
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<obj_property name="ElementShortName">FUJ[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">FUJ[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/FUB" type="array">
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||||||
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<obj_property name="ElementShortName">FUB[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">FUB[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/AddiOut" type="array">
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||||||
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<obj_property name="ElementShortName">AddiOut[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">AddiOut[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/AluOut" type="array">
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||||||
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<obj_property name="ElementShortName">AluOut[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">AluOut[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/RFIn" type="array">
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||||||
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<obj_property name="ElementShortName">RFIn[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">RFIn[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/dataMemOut" type="array">
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||||||
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<obj_property name="ElementShortName">dataMemOut[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">dataMemOut[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/SE1N" type="array">
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||||||
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<obj_property name="ElementShortName">SE1N[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">SE1N[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/SE2N" type="array">
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||||||
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<obj_property name="ElementShortName">SE2N[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">SE2N[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/SE3N" type="array">
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||||||
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<obj_property name="ElementShortName">SE3N[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">SE3N[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/bankOP" type="array">
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||||||
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<obj_property name="ElementShortName">bankOP[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">bankOP[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/jumpNeg" type="array">
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||||||
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<obj_property name="ElementShortName">jumpNeg[8:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">jumpNeg[8:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/aluOp" type="array">
|
||||||
|
<obj_property name="ElementShortName">aluOp[3:0]</obj_property>
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||||||
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<obj_property name="ObjectShortName">aluOp[3:0]</obj_property>
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||||||
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</wvobject>
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||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/FU" type="array">
|
||||||
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<obj_property name="ElementShortName">FU[2:0]</obj_property>
|
||||||
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<obj_property name="ObjectShortName">FU[2:0]</obj_property>
|
||||||
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</wvobject>
|
||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/bankS" type="array">
|
||||||
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<obj_property name="ElementShortName">bankS[1:0]</obj_property>
|
||||||
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<obj_property name="ObjectShortName">bankS[1:0]</obj_property>
|
||||||
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</wvobject>
|
||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/addiS" type="logic">
|
||||||
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<obj_property name="ElementShortName">addiS</obj_property>
|
||||||
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<obj_property name="ObjectShortName">addiS</obj_property>
|
||||||
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</wvobject>
|
||||||
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<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/RegEn" type="logic">
|
||||||
|
<obj_property name="ElementShortName">RegEn</obj_property>
|
||||||
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<obj_property name="ObjectShortName">RegEn</obj_property>
|
||||||
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</wvobject>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/loadS" type="logic">
|
||||||
|
<obj_property name="ElementShortName">loadS</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">loadS</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/fetchBranch" type="logic">
|
||||||
|
<obj_property name="ElementShortName">fetchBranch</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">fetchBranch</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/cout0" type="logic">
|
||||||
|
<obj_property name="ElementShortName">cout0</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">cout0</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/cout1" type="logic">
|
||||||
|
<obj_property name="ElementShortName">cout1</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">cout1</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/link" type="logic">
|
||||||
|
<obj_property name="ElementShortName">link</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">link</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/js" type="logic">
|
||||||
|
<obj_property name="ElementShortName">js</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">js</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/EM/dataMemEn" type="logic">
|
||||||
|
<obj_property name="ElementShortName">dataMemEn</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">dataMemEn</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
</wvobject>
|
||||||
<wvobject type="divider" fp_name="divider431">
|
<wvobject type="divider" fp_name="divider431">
|
||||||
<obj_property name="label">Divider</obj_property>
|
<obj_property name="label">Divider</obj_property>
|
||||||
<obj_property name="DisplayName">label</obj_property>
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
@@ -447,4 +693,29 @@
|
|||||||
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
|
<wvobject fp_name="group211" type="group">
|
||||||
|
<obj_property name="label">Pipe 2</obj_property>
|
||||||
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/pipe2/clk" type="logic">
|
||||||
|
<obj_property name="ElementShortName">clk</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">clk</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/pipe2/reset" type="logic">
|
||||||
|
<obj_property name="ElementShortName">reset</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">reset</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/pipe2/En" type="logic">
|
||||||
|
<obj_property name="ElementShortName">En</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">En</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/pipe2/Din" type="array">
|
||||||
|
<obj_property name="ElementShortName">Din[61:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">Din[61:0]</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/pipe2/Dout" type="array">
|
||||||
|
<obj_property name="ElementShortName">Dout[61:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">Dout[61:0]</obj_property>
|
||||||
|
<obj_property name="isExpanded"></obj_property>
|
||||||
|
</wvobject>
|
||||||
|
</wvobject>
|
||||||
</wave_config>
|
</wave_config>
|
||||||
|
|||||||
@@ -6,14 +6,14 @@ module dataMemory(
|
|||||||
output reg [8:0] readData
|
output reg [8:0] readData
|
||||||
);
|
);
|
||||||
|
|
||||||
reg [8:0] memory [1:0]; // Maximum of 512 memory locations
|
reg [8:0] memory [100:0]; // Maximum of 512 memory locations
|
||||||
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
|
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//Equation Solver Memory
|
// Equation Solver Memory
|
||||||
|
|
||||||
memory[0] <= 9'b000000001;
|
memory[0] <= 9'b000000001;
|
||||||
memory[1] <= 9'b000000010;
|
memory[1] <= 9'b000000010;
|
||||||
@@ -97,107 +97,107 @@ module dataMemory(
|
|||||||
|
|
||||||
// Program 1 Test Data
|
// Program 1 Test Data
|
||||||
|
|
||||||
memory[0] <= 9'd100;
|
// memory[0] <= 9'd100;
|
||||||
memory[1] <= 9'd58;
|
// memory[1] <= 9'd58;
|
||||||
memory[2] <= 9'd6;
|
// memory[2] <= 9'd6;
|
||||||
memory[3] <= 9'd12;
|
// memory[3] <= 9'd12;
|
||||||
memory[4] <= 9'b110110000; // -80
|
// memory[4] <= 9'b110110000; // -80
|
||||||
memory[5] <= 9'd17;
|
// memory[5] <= 9'd17;
|
||||||
memory[6] <= 9'b111011011; // -37
|
// memory[6] <= 9'b111011011; // -37
|
||||||
memory[7] <= 9'd25;
|
// memory[7] <= 9'd25;
|
||||||
memory[8] <= -9'd83; // -83
|
// memory[8] <= -9'd83; // -83
|
||||||
memory[9] <= -9'd98; // -98
|
// memory[9] <= -9'd98; // -98
|
||||||
memory[10] <= -9'd98; // -98
|
// memory[10] <= -9'd98; // -98
|
||||||
memory[11] <= -9'd74; // -74
|
// memory[11] <= -9'd74; // -74
|
||||||
memory[12] <= 9'd70;
|
// memory[12] <= 9'd70;
|
||||||
memory[13] <= -9'd38; // -38
|
// memory[13] <= -9'd38; // -38
|
||||||
memory[14] <= 9'd52;
|
// memory[14] <= 9'd52;
|
||||||
memory[15] <= -9'd96; // -96
|
// memory[15] <= -9'd96; // -96
|
||||||
memory[16] <= -9'd32; // -32
|
// memory[16] <= -9'd32; // -32
|
||||||
memory[17] <= -9'd93; // -93
|
// memory[17] <= -9'd93; // -93
|
||||||
memory[18] <= -9'd40; // -40
|
// memory[18] <= -9'd40; // -40
|
||||||
memory[19] <= 9'd59;
|
// memory[19] <= 9'd59;
|
||||||
memory[20] <= 9'd10;
|
// memory[20] <= 9'd10;
|
||||||
memory[21] <= 9'd81;
|
// memory[21] <= 9'd81;
|
||||||
memory[22] <= -9'd23; // -28
|
// memory[22] <= -9'd23; // -28
|
||||||
memory[23] <=- 9'd99; // -99
|
// memory[23] <=- 9'd99; // -99
|
||||||
memory[24] <= -9'd41; // -41
|
// memory[24] <= -9'd41; // -41
|
||||||
memory[25] <= 9'd33;
|
// memory[25] <= 9'd33;
|
||||||
memory[26] <= 9'd98;
|
// memory[26] <= 9'd98;
|
||||||
memory[27] <= 9'd73;
|
// memory[27] <= 9'd73;
|
||||||
memory[28] <= -9'd1; // -1
|
// memory[28] <= -9'd1; // -1
|
||||||
memory[29] <= 9'd28;
|
// memory[29] <= 9'd28;
|
||||||
memory[30] <= 9'd5;
|
// memory[30] <= 9'd5;
|
||||||
memory[31] <= -9'd74; // -74
|
// memory[31] <= -9'd74; // -74
|
||||||
memory[32] <= -9'd41; // -41
|
// memory[32] <= -9'd41; // -41
|
||||||
memory[33] <= 9'd41;
|
// memory[33] <= 9'd41;
|
||||||
memory[34] <= 9'd39;
|
// memory[34] <= 9'd39;
|
||||||
memory[35] <= 9'd62;
|
// memory[35] <= 9'd62;
|
||||||
memory[36] <= 9'd19;
|
// memory[36] <= 9'd19;
|
||||||
memory[37] <= -9'd40; // -40
|
// memory[37] <= -9'd40; // -40
|
||||||
memory[38] <= -9'd8; // -8
|
// memory[38] <= -9'd8; // -8
|
||||||
memory[39] <= 9'd92;
|
// memory[39] <= 9'd92;
|
||||||
memory[40] <= 9'd37;
|
// memory[40] <= 9'd37;
|
||||||
memory[41] <= 9'd50;
|
// memory[41] <= 9'd50;
|
||||||
memory[42] <= -9'd72; // -72
|
// memory[42] <= -9'd72; // -72
|
||||||
memory[43] <= -9'd5; // -5
|
// memory[43] <= -9'd5; // -5
|
||||||
memory[44] <= 9'd19;
|
// memory[44] <= 9'd19;
|
||||||
memory[45] <= 9'd58;
|
// memory[45] <= 9'd58;
|
||||||
memory[46] <= -9'd13; // -13
|
// memory[46] <= -9'd13; // -13
|
||||||
memory[47] <= 9'd0;
|
// memory[47] <= 9'd0;
|
||||||
memory[48] <= -9'd97; // -97
|
// memory[48] <= -9'd97; // -97
|
||||||
memory[49] <= 9'd54;
|
// memory[49] <= 9'd54;
|
||||||
memory[50] <= -9'd17; // -17
|
// memory[50] <= -9'd17; // -17
|
||||||
memory[51] <= -9'd83; // -83
|
// memory[51] <= -9'd83; // -83
|
||||||
memory[52] <= 9'd53;
|
// memory[52] <= 9'd53;
|
||||||
memory[53] <= 9'd82;
|
// memory[53] <= 9'd82;
|
||||||
memory[54] <= -9'd94; // -94
|
// memory[54] <= -9'd94; // -94
|
||||||
memory[55] <= -9'd77; // -77
|
// memory[55] <= -9'd77; // -77
|
||||||
memory[56] <= -9'd74; // -74
|
// memory[56] <= -9'd74; // -74
|
||||||
memory[57] <= -9'd52; // -52
|
// memory[57] <= -9'd52; // -52
|
||||||
memory[58] <= 9'd85;
|
// memory[58] <= 9'd85;
|
||||||
memory[59] <= -9'd65; // -65
|
// memory[59] <= -9'd65; // -65
|
||||||
memory[60] <= -9'd10; // -10
|
// memory[60] <= -9'd10; // -10
|
||||||
memory[61] <= -9'd45; // -45
|
// memory[61] <= -9'd45; // -45
|
||||||
memory[62] <= -9'd92; // -92
|
// memory[62] <= -9'd92; // -92
|
||||||
memory[63] <= -9'd30; // -30
|
// memory[63] <= -9'd30; // -30
|
||||||
memory[64] <= 9'd18;
|
// memory[64] <= 9'd18;
|
||||||
memory[65] <= -9'd95; // -95
|
// memory[65] <= -9'd95; // -95
|
||||||
memory[66] <= -9'd27; // -27
|
// memory[66] <= -9'd27; // -27
|
||||||
memory[67] <= -9'd74; // -74
|
// memory[67] <= -9'd74; // -74
|
||||||
memory[68] <= 9'd62;
|
// memory[68] <= 9'd62;
|
||||||
memory[69] <= 9'd64;
|
// memory[69] <= 9'd64;
|
||||||
memory[70] <= -9'd9; // -9
|
// memory[70] <= -9'd9; // -9
|
||||||
memory[71] <= 9'd66;
|
// memory[71] <= 9'd66;
|
||||||
memory[72] <= -9'd71; // -71
|
// memory[72] <= -9'd71; // -71
|
||||||
memory[73] <= -9'd31; // -31
|
// memory[73] <= -9'd31; // -31
|
||||||
memory[74] <= 9'd34;
|
// memory[74] <= 9'd34;
|
||||||
memory[75] <= 9'd12;
|
// memory[75] <= 9'd12;
|
||||||
memory[76] <= 9'd3;
|
// memory[76] <= 9'd3;
|
||||||
memory[77] <= 9'd82;
|
// memory[77] <= 9'd82;
|
||||||
memory[78] <= 9'd13;
|
// memory[78] <= 9'd13;
|
||||||
memory[79] <= -9'd78; // -78
|
// memory[79] <= -9'd78; // -78
|
||||||
memory[80] <= -9'd8; // -8
|
// memory[80] <= -9'd8; // -8
|
||||||
memory[81] <= 9'd88;
|
// memory[81] <= 9'd88;
|
||||||
memory[82] <= 9'd42;
|
// memory[82] <= 9'd42;
|
||||||
memory[83] <= 9'd42;
|
// memory[83] <= 9'd42;
|
||||||
memory[84] <= 9'd21;
|
// memory[84] <= 9'd21;
|
||||||
memory[85] <= -9'd44; // -44
|
// memory[85] <= -9'd44; // -44
|
||||||
memory[86] <= 9'd30;
|
// memory[86] <= 9'd30;
|
||||||
memory[87] <= -9'd93; // -93
|
// memory[87] <= -9'd93; // -93
|
||||||
memory[88] <= 9'd2;
|
// memory[88] <= 9'd2;
|
||||||
memory[89] <= -9'd34; // -34
|
// memory[89] <= -9'd34; // -34
|
||||||
memory[90] <= 9'd92;
|
// memory[90] <= 9'd92;
|
||||||
memory[91] <= -9'd45; // -45
|
// memory[91] <= -9'd45; // -45
|
||||||
memory[92] <= 9'd26;
|
// memory[92] <= 9'd26;
|
||||||
memory[93] <= -9'd79; // -79
|
// memory[93] <= -9'd79; // -79
|
||||||
memory[94] <= 9'd43;
|
// memory[94] <= 9'd43;
|
||||||
memory[95] <= -9'd25; // -25
|
// memory[95] <= -9'd25; // -25
|
||||||
memory[96] <= -9'd24; // -24
|
// memory[96] <= -9'd24; // -24
|
||||||
memory[97] <= -9'd25; // -25
|
// memory[97] <= -9'd25; // -25
|
||||||
memory[98] <= -9'd19; // -19
|
// memory[98] <= -9'd19; // -19
|
||||||
memory[99] <= -9'd49; // -49
|
// memory[99] <= -9'd49; // -49
|
||||||
memory[100] <= -9'd8; // -8
|
// memory[100] <= -9'd8; // -8
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -5,7 +5,7 @@ module instructionMemory(
|
|||||||
output reg [8:0] readData
|
output reg [8:0] readData
|
||||||
);
|
);
|
||||||
|
|
||||||
reg [8:0] memory [8:0]; // Maximum of 512 memory locations
|
reg [8:0] memory [100:0]; // Maximum of 512 memory locations
|
||||||
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
|
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
@@ -20,7 +20,7 @@ module instructionMemory(
|
|||||||
memory[7] <= 9'b111100000; //shift left
|
memory[7] <= 9'b111100000; //shift left
|
||||||
memory[8] <= 9'b111100000; //shift left
|
memory[8] <= 9'b111100000; //shift left
|
||||||
|
|
||||||
// //Testing all instructions
|
//Testing all instructions
|
||||||
// memory[6] <= 9'b010100011; //sub
|
// memory[6] <= 9'b010100011; //sub
|
||||||
// memory[7] <= 9'b011001011; //addi
|
// memory[7] <= 9'b011001011; //addi
|
||||||
// memory[8] <= 9'b011110000; //slt
|
// memory[8] <= 9'b011110000; //slt
|
||||||
@@ -209,8 +209,80 @@ module instructionMemory(
|
|||||||
// memory[60] <= 9'b101000110; //banks R0, 3
|
// memory[60] <= 9'b101000110; //banks R0, 3
|
||||||
// memory[61] <= 9'b100100000; //j Win
|
// memory[61] <= 9'b100100000; //j Win
|
||||||
// memory[62] <= 9'b000000000; //Win: halt
|
// memory[62] <= 9'b000000000; //Win: halt
|
||||||
|
|
||||||
|
|
||||||
|
// Basic Instruction Testing
|
||||||
|
|
||||||
|
// memory[0] <= 9'b000000001; // nop
|
||||||
|
// memory[1] <= 9'b010000000; // zero $a
|
||||||
|
// memory[2] <= 9'b000000001; // nop
|
||||||
|
// memory[3] <= 9'b000000001; // nop
|
||||||
|
// memory[4] <= 9'b000100000; // lb $a, $a
|
||||||
|
// memory[5] <= 9'b000000001; // nop
|
||||||
|
// memory[6] <= 9'b000000001; // nop
|
||||||
|
// memory[7] <= 9'b011000011; // addi $a, 3
|
||||||
|
// memory[8] <= 9'b000000001; // nop
|
||||||
|
// memory[9] <= 9'b000000001; // nop
|
||||||
|
// memory[10] <= 9'b000101010; // lb $b, $b
|
||||||
|
// memory[11] <= 9'b000110100; // lb $c, $c
|
||||||
|
// memory[12] <= 9'b000111110; // lb $d, $d
|
||||||
|
// memory[13] <= 9'b000000001; // nop
|
||||||
|
// memory[14] <= 9'b000000001; // nop
|
||||||
|
// memory[15] <= 9'b011001011; // addi $b, 3
|
||||||
|
// memory[16] <= 9'b011010011; // addi $c, 3
|
||||||
|
// memory[17] <= 9'b000000001; // nop
|
||||||
|
// memory[18] <= 9'b011011011; // addi $d, 3
|
||||||
|
// memory[19] <= 9'b; //
|
||||||
|
// memory[20] <= 9'b011000100; // addi $a, -4
|
||||||
|
// memory[21] <= 9'b000000001; // nop
|
||||||
|
// memory[22] <= 9'b000000001; // nop
|
||||||
|
// memory[23] <= 9'b010110110; // add $c, $d
|
||||||
|
// memory[24] <= 9'b010101001; // sub $b, $a
|
||||||
|
// memory[25] <= 9'b000000001; // nop
|
||||||
|
// memory[26] <= 9'b000000001; // nop
|
||||||
|
// memory[27] <= 9'b; //
|
||||||
|
// memory[28] <= 9'b; //
|
||||||
|
// memory[29] <= 9'b; //
|
||||||
|
// memory[30] <= 9'b; //
|
||||||
|
// memory[31] <= 9'b; //
|
||||||
|
// memory[32] <= 9'b; //
|
||||||
|
// memory[33] <= 9'b; //
|
||||||
|
// memory[34] <= 9'b; //
|
||||||
|
// memory[35] <= 9'b; //
|
||||||
|
// memory[36] <= 9'b; //
|
||||||
|
// memory[37] <= 9'b; //
|
||||||
|
// memory[38] <= 9'b; //
|
||||||
|
// memory[39] <= 9'b; //
|
||||||
|
// memory[40] <= 9'b; //
|
||||||
|
// memory[41] <= 9'b; //
|
||||||
|
// memory[42] <= 9'b; //
|
||||||
|
// memory[43] <= 9'b; //
|
||||||
|
// memory[44] <= 9'b; //
|
||||||
|
// memory[45] <= 9'b; //
|
||||||
|
// memory[46] <= 9'b; //
|
||||||
|
// memory[47] <= 9'b; //
|
||||||
|
// memory[48] <= 9'b; //
|
||||||
|
// memory[49] <= 9'b; //
|
||||||
|
// memory[50] <= 9'b; //
|
||||||
|
// memory[51] <= 9'b; //
|
||||||
|
// memory[52] <= 9'b; //
|
||||||
|
// memory[53] <= 9'b; //
|
||||||
|
// memory[54] <= 9'b; //
|
||||||
|
// memory[55] <= 9'b; //
|
||||||
|
// memory[56] <= 9'b; //
|
||||||
|
// memory[57] <= 9'b; //
|
||||||
|
// memory[58] <= 9'b; //
|
||||||
|
// memory[59] <= 9'b; //
|
||||||
|
// memory[60] <= 9'b; //
|
||||||
|
// memory[61] <= 9'b; //
|
||||||
|
// memory[62] <= 9'b; //
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
always @ (address)
|
always @ (address)
|
||||||
|
|||||||
@@ -31,7 +31,7 @@
|
|||||||
<Option Name="EnableBDX" Val="FALSE"/>
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
<Option Name="DSAVendor" Val="xilinx"/>
|
<Option Name="DSAVendor" Val="xilinx"/>
|
||||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||||
<Option Name="WTXSimLaunchSim" Val="386"/>
|
<Option Name="WTXSimLaunchSim" Val="408"/>
|
||||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
|||||||
Reference in New Issue
Block a user