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Made 16:1 MUX for ALU's 4-bit opcode

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WilliamMiceli
2019-03-12 11:08:22 -04:00
parent 9d759edbec
commit 1c5e79c1ec
1 changed files with 108 additions and 0 deletions
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108
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -455,6 +455,114 @@ module mux_8_1_tb();
end
endmodule
module mux_16_1(
input wire [3:0] switch,
input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,
output reg [8:0] out);
always @(A,B,C,D,E,F,G,H,switch) begin
case (switch)
4'b0000 : out = A;
4'b0001 : out = B;
4'b0010 : out = C;
4'b0011 : out = D;
4'b0100 : out = E;
4'b0101 : out = F;
4'b0110 : out = G;
4'b0111 : out = H;
4'b1000 : out = I;
4'b1001 : out = J;
4'b1010 : out = K;
4'b1011 : out = L;
4'b1100 : out = M;
4'b1101 : out = N;
4'b1110 : out = O;
4'b1111 : out = P;
default : out = 9'bxxxxxxxxx;
endcase
end
endmodule
//testbench
module mux_16_1_tb();
reg [2:0] switch;
reg [8:0] a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p;
wire [8:0] out;
mux_16_1 tb0(
.switch(switch),
.A(a),
.B(b),
.C(c),
.D(d),
.E(e),
.F(f),
.G(g),
.H(h),
.I(i),
.J(j),
.K(k),
.L(l),
.M(m),
.N(n),
.O(o),
.P(p),
.out(out));
initial begin
switch = 4'b0000;
a = 9'b000000101;
b = 9'b000111100;
c = 9'b001001001;
d = 9'b100110000;
e = 9'b010000101;
f = 9'b010111100;
g = 9'b011001001;
h = 9'b111000000;
i = 9'b100100101;
j = 9'b000001100;
k = 9'b001001001;
l = 9'b100110011;
m = 9'b010111101;
n = 9'b010110100;
o = 9'b100101001;
p = 9'b111001100;
#5
switch = 4'b0001;
#5
switch = 4'b0010;
#5
switch = 4'b0011;
#5
switch = 4'b0100;
#5
switch = 4'b0101;
#5
switch = 4'b0110;
#5
switch = 4'b0111;
#5
switch = 4'b1000;
#5
switch = 4'b1001;
#5
switch = 4'b1010;
#5
switch = 4'b1011;
#5
switch = 4'b1100;
#5
switch = 4'b1101;
#5
switch = 4'b1110;
#5
switch = 4'b1111;
#5
$finish;
end
endmodule
module nor_9bit(
input wire [8:0] A,
input wire [8:0] B,