Removed references to CLK, as not needed; simplified testbench a little

lab2CA.srcs/sources_1/new/instructionMemory.v

@@ -1,7 +1,6 @@
 `timescale 1ns / 1ps
 
 module instructionMemory(
-    input wire clk,
     input wire [8:0] address,
     output reg [8:0] readData
     );
@@ -216,19 +215,10 @@ endmodule
 
 
 module instructionMemory_tb();
-    reg clk;
     reg [8:0] address;
     wire [8:0] readData;
     
-        initial begin
-        clk = 1'b0;
-    end
-    always begin
-        #5 clk = ~clk; // Period to be determined
-    end
-    
     instructionMemory iM0(
-        .clk(clk),
         .address(address),
         .readData(readData)
     );