Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.srcs/sources_1/new/BasicModules.v

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -164,9 +164,26 @@ module gen_clock();
     end
 endmodule
 
+<<<<<<< HEAD
 <<<<<<< HEAD
 //To enable register, input 00 to En, register is always outputting contents
 =======
+=======
+module mux_2_1(input wire switch,
+           input wire [8:0] A,B,
+           output reg [8:0] out);
+           
+    always @(A,B,switch) begin
+        case (switch)
+            2'b00 : out = A;
+            2'b01 : out = B;
+            default : out = 9'bxxxxxxxxx;
+        endcase
+    end
+
+endmodule
+
+>>>>>>> b2eb0da26cf8a205e02981e2a7c6a774e8d18e02
 module mux_4_1(input wire [1:0] switch,
            input wire [8:0] A,B,C,D,
            output reg [8:0] out);

lab2CA.srcs/sources_1/new/FetchUnit.v

@@ -1,27 +1,32 @@
 `timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date: 02/15/2019 12:19:52 PM
-// Design Name: 
-// Module Name: FetchUnit
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-// 
-//////////////////////////////////////////////////////////////////////////////////
 
 
-module FetchUnit(input wire clk,
+module FetchUnit(input wire clk, reset, op_idx,
+                 input wire [1:0] write_index,
                  input wire [8:0] AddrIn,
                  output wire [8:0] AddrOut);
-
-endmodule
+  
+    //Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a) 
+    wire [8:0] progC_out, result_a, result_m;
+    
+    register PC(
+        .clk(clk),
+        .reset(reset),
+        .En({write_index[0], write_index[1]}),
+        .Din(result_m),
+        .Dout(progC_out));
+    //Adds 1 to the program counter
+    add_9bit PCAdder(
+        .A(progC_out),
+        .B(1'b1),
+        .Cin(1'b0),
+        .Sum(result_a));
+        
+    mux_2_1 PCmux(
+        .A(AddrIn),
+        .B(result_a),
+        .out(result_m),
+        .switch(op_idx));
+        
+        
+endmodule

lab2CA.srcs/sources_1/new/lab2testing.v

@@ -56,4 +56,29 @@ module regFile(input wire clk, reset,
         .D(r3_out),
         .switch(op1_idx));
     
-endmodule
+<<<<<<< Updated upstream
+endmodule
+=======
+endmodule
+
+module register(input wire clk, reset,
+                input wire [1:0] En,
+                input wire [7:0] Din,
+                output reg [7:0] Dout);
+
+endmodule
+
+module MUX();
+
+endmodule
+
+module fetchUnit(input wire clk, reset, write_en);
+    register progcount(
+        .clk(clk),
+        .reset(reset),
+        .En(),
+        .Din(),
+        .Dout());
+
+endmodule
+>>>>>>> Stashed changes