32 lines
794 B
Verilog
32 lines
794 B
Verilog
`timescale 1ns / 1ps
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module FetchUnit(input wire clk, reset, op_idx,
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input wire [1:0] write_index,
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input wire [8:0] AddrIn,
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output wire [8:0] AddrOut);
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//Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a)
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wire [8:0] progC_out, result_a, result_m;
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register PC(
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.clk(clk),
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.reset(reset),
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.En({write_index[0], write_index[1]}),
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.Din(result_m),
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.Dout(progC_out));
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//Adds 1 to the program counter
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add_9bit PCAdder(
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.A(progC_out),
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.B(1'b1),
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.Cin(1'b0),
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.Sum(result_a));
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mux_2_1 PCmux(
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.A(AddrIn),
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.B(result_a),
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.out(result_m),
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.switch(op_idx));
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endmodule |