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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

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# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.srcs/sources_1/new/BasicModules.v
This commit is contained in:
jose.rodriguezlabra committed 2019-02-16 12:39:15 -05:00
2 parents 9aa7a5f0b0 b2eb0da26c
commit 22bf2728ba
4 files changed
+168 -20
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lab2CA.cache/wt/webtalk_pa.xml
+101
View File
@@ -3,7 +3,15 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<<<<<<< HEAD
<application name="pa" timeStamp="Sat Feb 16 12:35:58 2019"> <application name="pa" timeStamp="Sat Feb 16 12:35:58 2019">
=======
<<<<<<< Updated upstream
<application name="pa" timeStamp="Fri Feb 15 17:51:37 2019">
=======
<application name="pa" timeStamp="Sat Feb 16 11:50:37 2019">
>>>>>>> Stashed changes
>>>>>>> b2eb0da26cf8a205e02981e2a7c6a774e8d18e02
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="ea51e471068f44c38a9f8c3803367e5e" type="ProjectID"/> <property name="ProjectID" value="ea51e471068f44c38a9f8c3803367e5e" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/> <property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -16,6 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/> <property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/> <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item> </item>
<<<<<<< HEAD
<item name="Gui Handlers"> <item name="Gui Handlers">
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="2" type="GuiHandlerData"/> <property name="FileSetPanel_FILE_SET_PANEL_TREE" value="2" type="GuiHandlerData"/>
</item> </item>
@@ -23,6 +32,98 @@ This means code written to parse this file will need to be revisited each subseq
<property name="GuiMode" value="32" type="GuiMode"/> <property name="GuiMode" value="32" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/> <property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="27" type="TclMode"/> <property name="TclMode" value="27" type="TclMode"/>
=======
<item name="Java Command Handlers">
<property name="AddSources" value="3" type="JavaHandler"/>
<property name="CloseProject" value="1" type="JavaHandler"/>
<property name="EditDelete" value="1" type="JavaHandler"/>
<<<<<<< Updated upstream
<property name="OpenProject" value="1" type="JavaHandler"/>
<property name="RunSchematic" value="1" type="JavaHandler"/>
<property name="RunSynthesis" value="3" type="JavaHandler"/>
<property name="SetTopNode" value="5" type="JavaHandler"/>
<property name="ShowView" value="2" type="JavaHandler"/>
<property name="ToggleSelectAreaMode" value="1" type="JavaHandler"/>
<property name="ToggleViewNavigator" value="4" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="2" type="JavaHandler"/>
<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="AddSrcWizard_SPECIFY_HDL_NETLIST_BLOCK_DESIGN" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="10" type="GuiHandlerData"/>
<property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="65" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="1" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="1" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="7" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="1" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="4" type="GuiHandlerData"/>
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="1" type="GuiHandlerData"/>
=======
<property name="NewProject" value="2" type="JavaHandler"/>
<property name="OpenProject" value="4" type="JavaHandler"/>
<property name="SaveProjectAs" value="1" type="JavaHandler"/>
<property name="ToolsSettings" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_OK" value="7" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="3" type="GuiHandlerData"/>
<property name="FPGAChooser_CATEGORY" value="1" type="GuiHandlerData"/>
<property name="FPGAChooser_FAMILY" value="2" type="GuiHandlerData"/>
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
<property name="FPGAChooser_PACKAGE" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="40" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="1" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="2" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="3" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="12" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="16" type="GuiHandlerData"/>
>>>>>>> Stashed changes
<property name="PACommandNames_ADD_SOURCES" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SELECT_AREA" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="5" type="GuiHandlerData"/>
<property name="PACommandNames_TOGGLE_VIEW_NAV" value="4" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="9" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="2" type="GuiHandlerData"/>
<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="2" type="GuiHandlerData"/>
<property name="ProjectDashboardView_DASHBOARD" value="2" type="GuiHandlerData"/>
<property name="ProjectDashboardView_TABBED_PANE" value="2" type="GuiHandlerData"/>
<property name="ProjectTab_RELOAD" value="4" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="1" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="1" type="GuiHandlerData"/>
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="2" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="5" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
</item>
<item name="Other">
<<<<<<< Updated upstream
<property name="GuiMode" value="60" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="59" type="TclMode"/>
=======
<property name="GuiMode" value="3" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="2" type="TclMode"/>
>>>>>>> Stashed changes
>>>>>>> b2eb0da26cf8a205e02981e2a7c6a774e8d18e02
</item> </item>
</section> </section>
</application> </application>
lab2CA.srcs/sources_1/new/BasicModules.v
+17
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@@ -164,9 +164,26 @@ module gen_clock();
end end
endmodule endmodule
<<<<<<< HEAD
<<<<<<< HEAD <<<<<<< HEAD
//To enable register, input 00 to En, register is always outputting contents //To enable register, input 00 to En, register is always outputting contents
======= =======
=======
module mux_2_1(input wire switch,
input wire [8:0] A,B,
output reg [8:0] out);
always @(A,B,switch) begin
case (switch)
2'b00 : out = A;
2'b01 : out = B;
default : out = 9'bxxxxxxxxx;
endcase
end
endmodule
>>>>>>> b2eb0da26cf8a205e02981e2a7c6a774e8d18e02
module mux_4_1(input wire [1:0] switch, module mux_4_1(input wire [1:0] switch,
input wire [8:0] A,B,C,D, input wire [8:0] A,B,C,D,
output reg [8:0] out); output reg [8:0] out);
lab2CA.srcs/sources_1/new/FetchUnit.v
+25 -20
View File
@@ -1,27 +1,32 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/15/2019 12:19:52 PM
// Design Name:
// Module Name: FetchUnit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FetchUnit(input wire clk, module FetchUnit(input wire clk, reset, op_idx,
input wire [1:0] write_index,
input wire [8:0] AddrIn, input wire [8:0] AddrIn,
output wire [8:0] AddrOut); output wire [8:0] AddrOut);
//Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a)
wire [8:0] progC_out, result_a, result_m;
register PC(
.clk(clk),
.reset(reset),
.En({write_index[0], write_index[1]}),
.Din(result_m),
.Dout(progC_out));
//Adds 1 to the program counter
add_9bit PCAdder(
.A(progC_out),
.B(1'b1),
.Cin(1'b0),
.Sum(result_a));
mux_2_1 PCmux(
.A(AddrIn),
.B(result_a),
.out(result_m),
.switch(op_idx));
endmodule endmodule
lab2CA.srcs/sources_1/new/lab2testing.v
+25
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@@ -56,4 +56,29 @@ module regFile(input wire clk, reset,
.D(r3_out), .D(r3_out),
.switch(op1_idx)); .switch(op1_idx));
<<<<<<< Updated upstream
endmodule endmodule
=======
endmodule
module register(input wire clk, reset,
input wire [1:0] En,
input wire [7:0] Din,
output reg [7:0] Dout);
endmodule
module MUX();
endmodule
module fetchUnit(input wire clk, reset, write_en);
register progcount(
.clk(clk),
.reset(reset),
.En(),
.Din(),
.Dout());
endmodule
>>>>>>> Stashed changes