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WilliamMiceli
2019-02-15 14:34:59 -05:00
parent 7aa2cfff2a
commit 337bf5cf13
2 changed files with 0 additions and 40 deletions
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20
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -1,24 +1,4 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/15/2019 12:18:27 PM
// Design Name:
// Module Name: BasicModules
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BasicModules(); module BasicModules();
endmodule endmodule

20
lab2CA.srcs/sources_1/new/RegFile.v
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@@ -1,24 +1,4 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/15/2019 12:21:16 PM
// Design Name:
// Module Name: RegFile
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RegFile(input wire clk, reset, module RegFile(input wire clk, reset,
input wire [1:0] write_index, op0_idx, op1_idx, input wire [1:0] write_index, op0_idx, op1_idx,