fetch unit

Should be done. also added 2 to 1 mux

lab2CA.srcs/sources_1/new/lab2testing.v

@@ -56,4 +56,29 @@ module regFile(input wire clk, reset,
         .D(r3_out),
         .switch(op1_idx));
     
-endmodule
+<<<<<<< Updated upstream
+endmodule
+=======
+endmodule
+
+module register(input wire clk, reset,
+                input wire [1:0] En,
+                input wire [7:0] Din,
+                output reg [7:0] Dout);
+
+endmodule
+
+module MUX();
+
+endmodule
+
+module fetchUnit(input wire clk, reset, write_en);
+    register progcount(
+        .clk(clk),
+        .reset(reset),
+        .En(),
+        .Din(),
+        .Dout());
+
+endmodule
+>>>>>>> Stashed changes