Added result, found that waiting 50000 ns is not necessary, as there's a button for it

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -203,6 +203,7 @@ endmodule
 
 module CPU9bits_tb();
     reg clk, reset;
+    reg [8:0] result;
     wire done;
 
     always
@@ -211,14 +212,14 @@ module CPU9bits_tb();
     CPU9bits CPU9bits0(
         .reset(reset),
         .clk(clk),
-        .done(done));
+        .done(done)
+        );
         
     initial begin
         clk = 1'b0;
         reset = 1'b1;
         #5
         reset = 1'b0;
-        #50000
     
 //        instruction = 9'b000100000;
 //        reset = 1'b1;