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WilliamMiceli
2019-04-06 16:06:49 -04:00
parent b3e2adb097
commit 4aad1aaaf7
1 changed files with 154 additions and 152 deletions
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306
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -13,71 +13,72 @@ module ControlUnit(
case(instIn)
4'b0000: // Halt/NOP
begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0001: // Load Byte
begin
aluOut <= 4'b0000;
mem <= 1'b1;
dataMemEn <= 1'b0; // Disabled
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b1;
dataMemEn <= 1'b0; // Disabled
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0010: // Store Byte
begin
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b1; // Enabled
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b1; // Enabled
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0011: // Link
begin
halt <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
halt <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
end
4'b0100: // Zero
begin
aluOut <= 4'b1011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b1011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0101: // Add/Subtract
if(functBit == 1) begin // Subtract
if(functBit == 1) // Subtract
begin
aluOut <= 4'b0001;
RegEn <= 1'b0;
FU <= 3'b001;
@@ -88,8 +89,9 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin // Add
end
else // Add
begin
aluOut <= 4'b0000;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
@@ -100,114 +102,114 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
end
4'b0110: // Add Immediate
begin
aluOut <= 4'b1010;
addi <= 1'b1;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b1010;
addi <= 1'b1;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0111: // Set if Less Than
begin
aluOut <= 4'b1001;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b1001;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1000: // Jump to Register
begin
aluOut <= 4'b0000;
FU <= 3'b000;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b0000;
FU <= 3'b000;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1001: // Jump Forward
begin
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1010: // Bank Load/Bank Store
begin
halt <= 1'b0;
RegEn <= !functBit;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
dataMemEn <= 1'b0; // Disabled
mem <= 1'b0;
link <= 1'b0;
bank <= {functBit,functBit};
js <= 1'b0;
halt <= 1'b0;
RegEn <= !functBit;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
dataMemEn <= 1'b0; // Disabled
mem <= 1'b0;
link <= 1'b0;
bank <= {functBit,functBit};
js <= 1'b0;
end
4'b1011: // Jump Backward
begin
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
end
4'b1100: // Branch if Zero
begin
aluOut <= 4'b1010;
FU <= 3'b110;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b1010;
FU <= 3'b110;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1101: // NOR
begin
aluOut <= 4'b0011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b0011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1110: // OR/AND
if(functBit == 1) // AND
begin
begin
aluOut <= 4'b0100;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
@@ -218,9 +220,9 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
end
else // OR
begin
begin
aluOut <= 4'b0010;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
@@ -231,10 +233,10 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
end
4'b1111: // Shift Right Logical/Shift Left Logical
if(functBit == 1) // Shift Right Logical
begin
begin
aluOut <= 4'b0110;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
@@ -245,9 +247,9 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
end
else // Shift Left Logical
begin
begin
aluOut <= 4'b0101;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
@@ -258,19 +260,19 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
end
default:
begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001;
dataMemEn <= 1'b0; // Disabled
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001;
dataMemEn <= 1'b0; // Disabled
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
endcase
end