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Modified sensitivities for result; Vivado metadata

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WilliamMiceli
2019-03-30 15:59:43 -04:00
parent ea0111542a
commit 443d01eba1
45 changed files with 2585 additions and 124 deletions
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42
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Mar 29 17:10:43 2019
| Date : Sat Mar 30 15:53:22 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
@@ -30,11 +30,11 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 2 | 0 | 101400 | <0.01 |
| LUT as Logic | 2 | 0 | 101400 | <0.01 |
| Slice LUTs* | 73 | 0 | 101400 | 0.07 |
| LUT as Logic | 73 | 0 | 101400 | 0.07 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 3 | 0 | 202800 | <0.01 |
| Register as Flip Flop | 3 | 0 | 202800 | <0.01 |
| Slice Registers | 21 | 0 | 202800 | 0.01 |
| Register as Flip Flop | 21 | 0 | 202800 | 0.01 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
@@ -57,20 +57,21 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 3 | Yes | Reset | - |
| 21 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 0 | 0 | 650 | 0.00 |
+----------------+------+-------+-----------+-------+
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 1 | 0 | 650 | 0.15 |
| RAMB18E1 only | 1 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -90,7 +91,7 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 3 | 0 | 285 | 1.05 |
| Bonded IOB | 12 | 0 | 285 | 4.21 |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
@@ -151,12 +152,15 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 3 | Flop & Latch |
| LUT3 | 2 | LUT |
| LUT6 | 37 | LUT |
| LUT4 | 27 | LUT |
| FDRE | 21 | Flop & Latch |
| OBUF | 10 | IO |
| LUT5 | 10 | LUT |
| LUT2 | 4 | LUT |
| LUT3 | 3 | LUT |
| IBUF | 2 | IO |
| OBUF | 1 | IO |
| LUT4 | 1 | LUT |
| LUT2 | 1 | LUT |
| RAMB18E1 | 1 | Block Memory |
| BUFG | 1 | Clock |
+----------+------+---------------------+