Removed CLK, as it is not needed

2019-03-29 16:16:36 -04:00
parent 44c057e40d
commit 445f5ce830
1 changed files with 0 additions and 1 deletions
--- a/lab2CA.srcs/sources_1/new/CPU9bits.v
+++ b/lab2CA.srcs/sources_1/new/CPU9bits.v
@@ -12,7 +12,6 @@ module CPU9bits(
    wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn;
        
    instructionMemory iM(
-        .clk(clk),
        .address(PCout),
        .readData(instr)
        );