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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

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# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/CPU9bits.v
#	lab2CA.srcs/sources_1/new/dataMemory.v
This commit is contained in:
WilliamMiceli
2019-03-24 19:31:28 -04:00
parent 7490815502 65b951cf82
commit 5353c8c22e
9 changed files with 22 additions and 295 deletions
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4
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -186,7 +186,7 @@ module CPU9bits_tb();
.done(done));
initial begin
#10
#5
reset = 1'b1;
#10
reset = 1'b0;
@@ -216,4 +216,4 @@ module CPU9bits_tb();
$finish;
end
endmodule
endmodule

8
lab2CA.srcs/sources_1/new/dataMemory.v
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@@ -9,6 +9,10 @@ module dataMemory(
reg [8:0] memory [23:0];
initial begin
//Equation Solver Memory
memory[0] <= 9'b000000001;
memory[1] <= 9'b000000010;
// String Compare Memory
// memory[0] <= 9'b000000100;
// memory[1] <= 9'b000001000;
@@ -16,10 +20,10 @@ module dataMemory(
// memory[3] <= 9'b010101010;
// memory[4] <= 9'b000001111;
// memory[5] <= 9'b000000100;
// memory[6] <= 9'b000000011;
// memory[6] <= 9'b000000000;
// memory[7] <= 9'b000000111;
// memory[8] <= 9'b000001111;
// memory[9] <= 9'b000000100;
// memory[9] <= 9'b000000110;
// memory[10] <= 9'b000000010;
// memory[11] <= 9'b000000000;
// memory[12] <= 9'b000000000;

23
lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -10,12 +10,15 @@ module instructionMemory(
initial begin
//Equation Solver
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b000100000; //load
// memory[2] <= 9'b000101000; //load
// memory[3] <= 9'b010100010; //add
// memory[4] <= 9'b111100000; //shift left
// memory[5] <= 9'b111100000; //shift left
memory[0] <= 9'b000000000;
memory[1] <= 9'b011000000; //add0
memory[1] <= 9'b011001001; //add1
memory[1] <= 9'b000100000; //load
memory[2] <= 9'b000101000; //load
memory[3] <= 9'b010100010; //add
memory[4] <= 9'b111100000; //shift left
memory[5] <= 9'b111100000; //shift left
memory[6] <= 9'b000000000; //halt
// //Testing all instructions
// memory[6] <= 9'b010100011; //sub
@@ -74,7 +77,7 @@ module instructionMemory(
// memory[37] <= 9'b101000000;
// memory[38] <= 9'b101110111;
// memory[39] <= 9'b000000000;
// Bubble Sort
memory[0] <= 9'b000000001; // nop
@@ -210,8 +213,10 @@ module instructionMemory(
end
always@(address)begin
readData <= memory[address];
always@(address, clk)begin
if(clk == 1'b1)begin
readData <= memory[address];
end
end
endmodule