William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Lots

Browse Source 
Lots
This commit is contained in:
goochey
2019-02-16 17:40:18 -05:00
parent faf9f883dd
commit 54cccd419f
107 changed files with 6032 additions and 121 deletions
Download Patch File Download Diff File Expand all files Collapse all files

451
lab2CA.runs/impl_1/FetchUnit.vdi Normal file
View File

@@ -0,0 +1,451 @@
#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 17:35:59 2019
# Process ID: 3548
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log FetchUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FetchUnit.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit.vdi
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source FetchUnit.tcl -notrace
Command: link_design -top FetchUnit -part xc7k160tifbg484-2L
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 578.453 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 584.031 ; gain = 333.246
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.760 . Memory (MB): peak = 598.289 ; gain = 14.258
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 3da38fa8
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1160.113 ; gain = 561.824
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 3da38fa8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1256.469 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 3da38fa8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1256.469 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 3da38fa8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1256.469 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 3da38fa8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1256.469 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 3da38fa8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1256.469 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 3da38fa8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1256.469 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1256.469 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 3da38fa8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.098 . Memory (MB): peak = 1256.469 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 3da38fa8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1256.469 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 3da38fa8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 3da38fa8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1256.469 ; gain = 672.438
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx
Command: report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2dee624c
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1256.469 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: c3ac8419
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 17eb8b195
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 17eb8b195
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563
Phase 1 Placer Initialization | Checksum: 17eb8b195
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 17eb8b195
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.789 ; gain = 5.320
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2 Global Placement | Checksum: c93401db
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: c93401db
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 13d5628d5
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1566ae30c
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1566ae30c
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 179d3e6f9
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 179d3e6f9
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 179d3e6f9
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
Phase 3 Detail Placement | Checksum: 179d3e6f9
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 179d3e6f9
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 179d3e6f9
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 179d3e6f9
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1280.449 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 1f8cde3fa
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f8cde3fa
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
Ending Placer Task | Checksum: 12070b279
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980
INFO: [Common 17-83] Releasing license: Implementation
37 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1280.449 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 1280.449 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file FetchUnit_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1280.449 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1280.449 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 80d46943 ConstDB: 0 ShapeSum: 9f9c4936 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: c942aae2
Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1491.852 ; gain = 211.402
Post Restoration Checksum: NetGraph: 96738515 NumContArr: 32cf25cd Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: c942aae2
Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1496.797 ; gain = 216.348
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: c942aae2
Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1496.797 ; gain = 216.348
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: a27c41a8
Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1520.801 ; gain = 240.352
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 15301da77
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
Phase 4 Rip-up And Reroute | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
Phase 6 Post Hold Fix | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.00297689 %
Global Horizontal Routing Utilization = 0.00221654 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 25.2252%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 4b1641fa
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
49 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1520.801 ; gain = 240.352
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1520.801 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1520.801 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx
Command: report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx
Command: report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx
Command: report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
60 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file FetchUnit_route_status.rpt -pb FetchUnit_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file FetchUnit_timing_summary_routed.rpt -pb FetchUnit_timing_summary_routed.pb -rpx FetchUnit_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file FetchUnit_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file FetchUnit_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 17:37:11 2019...