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goochey
2019-02-16 17:40:18 -05:00
parent faf9f883dd
commit 54cccd419f
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lab2CA.runs/impl_1/FetchUnit_control_sets_placed.rpt Normal file
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:36:37 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt
| Design : FetchUnit
| Device : xc7k160ti
--------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 1 |
| Unused register locations in slices containing registers | 7 |
+----------------------------------------------------------+-------+
2. Histogram
------------
+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
| 9 | 1 |
+--------+--------------+
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 0 | 0 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 9 | 2 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 0 | 0 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+----------------+---------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------+---------------+------------------+------------------+----------------+
| clk_IBUF_BUFG | | reset_IBUF | 2 | 9 |
+----------------+---------------+------------------+------------------+----------------+