Lots

2019-02-16 17:40:18 -05:00
parent faf9f883dd
commit 54cccd419f
107 changed files with 6032 additions and 121 deletions
--- a/lab2CA.sim/sim_1/behav/xsim/alu_tb_vlog.prj
+++ b/lab2CA.sim/sim_1/behav/xsim/alu_tb_vlog.prj
@@ -0,0 +1,10 @@
+# compile verilog/system verilog design source files
+verilog xil_defaultlib  \
+"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
+"../../../../lab2CA.srcs/sources_1/new/ALU.v" \
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort