Lots
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goochey
11
lab2CA.sim/sim_1/impl/func/xsim/alu_tb.tcl
Normal file
11
lab2CA.sim/sim_1/impl/func/xsim/alu_tb.tcl
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@@ -0,0 +1,11 @@
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set curr_wave [current_wave_config]
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if { [string length $curr_wave] == 0 } {
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if { [llength [get_objects]] > 0} {
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add_wave /
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set_property needs_save false [current_wave_config]
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} else {
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send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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}
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}
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run 1000ns
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927
lab2CA.sim/sim_1/impl/func/xsim/alu_tb_func_impl.v
Normal file
927
lab2CA.sim/sim_1/impl/func/xsim/alu_tb_func_impl.v
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@@ -0,0 +1,927 @@
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// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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// Date : Sat Feb 16 16:48:37 2019
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// Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
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// Command : write_verilog -mode funcsim -nolib -force -file
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// C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/alu_tb_func_impl.v
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// Design : RegFile
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// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
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// or synthesized. This netlist cannot be used for SDF annotated simulation.
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// Device : xc7k160tifbg484-2L
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// --------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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(* ECO_CHECKSUM = "b4d7812f" *)
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(* NotValidForBitStream *)
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module RegFile
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(clk,
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reset,
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write_index,
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op0_idx,
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op1_idx,
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write_data,
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op0,
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op1);
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input clk;
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input reset;
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input [1:0]write_index;
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input [1:0]op0_idx;
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input [1:0]op1_idx;
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input [8:0]write_data;
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output [8:0]op0;
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output [8:0]op1;
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wire clk;
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wire clk_IBUF;
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wire clk_IBUF_BUFG;
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wire [8:0]op0;
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wire [8:0]op0_OBUF;
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wire \op0_OBUF[8]_inst_i_10_n_0 ;
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wire \op0_OBUF[8]_inst_i_11_n_0 ;
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wire \op0_OBUF[8]_inst_i_12_n_0 ;
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wire \op0_OBUF[8]_inst_i_6_n_0 ;
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wire \op0_OBUF[8]_inst_i_7_n_0 ;
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wire \op0_OBUF[8]_inst_i_8_n_0 ;
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wire \op0_OBUF[8]_inst_i_9_n_0 ;
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wire [1:0]op0_idx;
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wire [1:0]op0_idx_IBUF;
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wire [8:0]op1;
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wire [8:0]op1_OBUF;
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wire [1:0]op1_idx;
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wire [1:0]op1_idx_IBUF;
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wire \r0/_n_0 ;
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wire [8:0]r0_out;
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wire [8:0]r1_out;
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wire [8:0]r2_out;
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wire [8:0]r3_out;
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wire reset;
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wire reset_IBUF;
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wire [8:0]write_data;
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wire [8:0]write_data_IBUF;
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wire [1:0]write_index;
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wire [1:0]write_index_IBUF;
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BUFG clk_IBUF_BUFG_inst
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(.I(clk_IBUF),
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.O(clk_IBUF_BUFG));
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IBUF clk_IBUF_inst
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(.I(clk),
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.O(clk_IBUF));
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mux_4_1 m0
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(.op0_OBUF(op0_OBUF),
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.op0_idx_IBUF(op0_idx_IBUF),
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.r0_out(r0_out),
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.r1_out(r1_out),
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.r2_out(r2_out),
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.r3_out(r3_out));
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mux_4_1_0 m1
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(.op1_OBUF(op1_OBUF),
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.op1_idx_IBUF(op1_idx_IBUF),
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.r0_out(r0_out),
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.r1_out(r1_out),
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.r2_out(r2_out),
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.r3_out(r3_out));
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OBUF \op0_OBUF[0]_inst
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(.I(op0_OBUF[0]),
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.O(op0[0]));
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OBUF \op0_OBUF[1]_inst
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(.I(op0_OBUF[1]),
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.O(op0[1]));
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OBUF \op0_OBUF[2]_inst
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(.I(op0_OBUF[2]),
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.O(op0[2]));
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OBUF \op0_OBUF[3]_inst
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(.I(op0_OBUF[3]),
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.O(op0[3]));
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OBUF \op0_OBUF[4]_inst
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(.I(op0_OBUF[4]),
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.O(op0[4]));
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OBUF \op0_OBUF[5]_inst
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(.I(op0_OBUF[5]),
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.O(op0[5]));
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OBUF \op0_OBUF[6]_inst
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(.I(op0_OBUF[6]),
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.O(op0[6]));
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OBUF \op0_OBUF[7]_inst
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(.I(op0_OBUF[7]),
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.O(op0[7]));
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OBUF \op0_OBUF[8]_inst
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(.I(op0_OBUF[8]),
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.O(op0[8]));
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(* SOFT_HLUTNM = "soft_lutpair18" *)
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LUT2 #(
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.INIT(4'h4))
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\op0_OBUF[8]_inst_i_10
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(.I0(write_index_IBUF[0]),
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.I1(write_index_IBUF[1]),
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.O(\op0_OBUF[8]_inst_i_10_n_0 ));
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(* SOFT_HLUTNM = "soft_lutpair19" *)
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LUT2 #(
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.INIT(4'h8))
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\op0_OBUF[8]_inst_i_11
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(.I0(write_index_IBUF[0]),
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.I1(write_index_IBUF[1]),
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.O(\op0_OBUF[8]_inst_i_11_n_0 ));
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(* SOFT_HLUTNM = "soft_lutpair19" *)
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LUT2 #(
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.INIT(4'h4))
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\op0_OBUF[8]_inst_i_12
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(.I0(write_index_IBUF[1]),
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.I1(write_index_IBUF[0]),
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.O(\op0_OBUF[8]_inst_i_12_n_0 ));
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FDSE #(
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.INIT(1'b1))
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\op0_OBUF[8]_inst_i_6
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(.C(clk_IBUF_BUFG),
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.CE(1'b1),
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.D(\op0_OBUF[8]_inst_i_10_n_0 ),
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.Q(\op0_OBUF[8]_inst_i_6_n_0 ),
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.S(reset_IBUF));
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FDSE #(
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.INIT(1'b1))
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\op0_OBUF[8]_inst_i_7
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(.C(clk_IBUF_BUFG),
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.CE(1'b1),
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.D(\r0/_n_0 ),
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.Q(\op0_OBUF[8]_inst_i_7_n_0 ),
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.S(reset_IBUF));
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FDSE #(
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.INIT(1'b1))
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\op0_OBUF[8]_inst_i_8
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(.C(clk_IBUF_BUFG),
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.CE(1'b1),
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.D(\op0_OBUF[8]_inst_i_11_n_0 ),
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.Q(\op0_OBUF[8]_inst_i_8_n_0 ),
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.S(reset_IBUF));
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FDSE #(
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.INIT(1'b1))
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\op0_OBUF[8]_inst_i_9
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(.C(clk_IBUF_BUFG),
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.CE(1'b1),
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.D(\op0_OBUF[8]_inst_i_12_n_0 ),
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.Q(\op0_OBUF[8]_inst_i_9_n_0 ),
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.S(reset_IBUF));
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IBUF \op0_idx_IBUF[0]_inst
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(.I(op0_idx[0]),
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.O(op0_idx_IBUF[0]));
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IBUF \op0_idx_IBUF[1]_inst
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(.I(op0_idx[1]),
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.O(op0_idx_IBUF[1]));
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OBUF \op1_OBUF[0]_inst
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(.I(op1_OBUF[0]),
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.O(op1[0]));
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OBUF \op1_OBUF[1]_inst
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(.I(op1_OBUF[1]),
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.O(op1[1]));
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OBUF \op1_OBUF[2]_inst
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(.I(op1_OBUF[2]),
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.O(op1[2]));
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OBUF \op1_OBUF[3]_inst
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(.I(op1_OBUF[3]),
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.O(op1[3]));
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OBUF \op1_OBUF[4]_inst
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(.I(op1_OBUF[4]),
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.O(op1[4]));
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OBUF \op1_OBUF[5]_inst
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(.I(op1_OBUF[5]),
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.O(op1[5]));
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OBUF \op1_OBUF[6]_inst
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(.I(op1_OBUF[6]),
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.O(op1[6]));
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OBUF \op1_OBUF[7]_inst
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(.I(op1_OBUF[7]),
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.O(op1[7]));
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OBUF \op1_OBUF[8]_inst
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(.I(op1_OBUF[8]),
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.O(op1[8]));
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IBUF \op1_idx_IBUF[0]_inst
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(.I(op1_idx[0]),
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.O(op1_idx_IBUF[0]));
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IBUF \op1_idx_IBUF[1]_inst
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(.I(op1_idx[1]),
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.O(op1_idx_IBUF[1]));
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(* SOFT_HLUTNM = "soft_lutpair18" *)
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LUT2 #(
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.INIT(4'h1))
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\r0/
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(.I0(write_index_IBUF[0]),
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.I1(write_index_IBUF[1]),
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.O(\r0/_n_0 ));
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register r3
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(.clk_IBUF_BUFG(clk_IBUF_BUFG),
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.\op0_OBUF[8]_inst_i_1 (\op0_OBUF[8]_inst_i_7_n_0 ),
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.\op0_OBUF[8]_inst_i_1_0 (\op0_OBUF[8]_inst_i_6_n_0 ),
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.\op0_OBUF[8]_inst_i_1_1 (\op0_OBUF[8]_inst_i_9_n_0 ),
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.\op0_OBUF[8]_inst_i_1_2 (\op0_OBUF[8]_inst_i_8_n_0 ),
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.r0_out(r0_out),
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.r1_out(r1_out),
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.r2_out(r2_out),
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.r3_out(r3_out),
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.reset_IBUF(reset_IBUF),
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.write_data_IBUF(write_data_IBUF));
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IBUF reset_IBUF_inst
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(.I(reset),
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.O(reset_IBUF));
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IBUF \write_data_IBUF[0]_inst
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(.I(write_data[0]),
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.O(write_data_IBUF[0]));
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IBUF \write_data_IBUF[1]_inst
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(.I(write_data[1]),
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.O(write_data_IBUF[1]));
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IBUF \write_data_IBUF[2]_inst
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(.I(write_data[2]),
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.O(write_data_IBUF[2]));
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IBUF \write_data_IBUF[3]_inst
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(.I(write_data[3]),
|
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.O(write_data_IBUF[3]));
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IBUF \write_data_IBUF[4]_inst
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(.I(write_data[4]),
|
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.O(write_data_IBUF[4]));
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IBUF \write_data_IBUF[5]_inst
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(.I(write_data[5]),
|
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.O(write_data_IBUF[5]));
|
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IBUF \write_data_IBUF[6]_inst
|
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(.I(write_data[6]),
|
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.O(write_data_IBUF[6]));
|
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IBUF \write_data_IBUF[7]_inst
|
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(.I(write_data[7]),
|
||||
.O(write_data_IBUF[7]));
|
||||
IBUF \write_data_IBUF[8]_inst
|
||||
(.I(write_data[8]),
|
||||
.O(write_data_IBUF[8]));
|
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IBUF \write_index_IBUF[0]_inst
|
||||
(.I(write_index[0]),
|
||||
.O(write_index_IBUF[0]));
|
||||
IBUF \write_index_IBUF[1]_inst
|
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(.I(write_index[1]),
|
||||
.O(write_index_IBUF[1]));
|
||||
endmodule
|
||||
|
||||
module mux_4_1
|
||||
(op0_OBUF,
|
||||
r1_out,
|
||||
r0_out,
|
||||
r3_out,
|
||||
op0_idx_IBUF,
|
||||
r2_out);
|
||||
output [8:0]op0_OBUF;
|
||||
input [8:0]r1_out;
|
||||
input [8:0]r0_out;
|
||||
input [8:0]r3_out;
|
||||
input [1:0]op0_idx_IBUF;
|
||||
input [8:0]r2_out;
|
||||
|
||||
wire [8:0]op0_OBUF;
|
||||
wire [1:0]op0_idx_IBUF;
|
||||
wire [8:0]r0_out;
|
||||
wire [8:0]r1_out;
|
||||
wire [8:0]r2_out;
|
||||
wire [8:0]r3_out;
|
||||
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[0]_inst_i_1
|
||||
(.I0(r1_out[0]),
|
||||
.I1(r0_out[0]),
|
||||
.I2(r3_out[0]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[0]),
|
||||
.O(op0_OBUF[0]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[1]_inst_i_1
|
||||
(.I0(r1_out[1]),
|
||||
.I1(r0_out[1]),
|
||||
.I2(r3_out[1]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[1]),
|
||||
.O(op0_OBUF[1]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[2]_inst_i_1
|
||||
(.I0(r1_out[2]),
|
||||
.I1(r0_out[2]),
|
||||
.I2(r3_out[2]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[2]),
|
||||
.O(op0_OBUF[2]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[3]_inst_i_1
|
||||
(.I0(r1_out[3]),
|
||||
.I1(r0_out[3]),
|
||||
.I2(r3_out[3]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[3]),
|
||||
.O(op0_OBUF[3]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[4]_inst_i_1
|
||||
(.I0(r1_out[4]),
|
||||
.I1(r0_out[4]),
|
||||
.I2(r3_out[4]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[4]),
|
||||
.O(op0_OBUF[4]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[5]_inst_i_1
|
||||
(.I0(r1_out[5]),
|
||||
.I1(r0_out[5]),
|
||||
.I2(r3_out[5]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[5]),
|
||||
.O(op0_OBUF[5]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[6]_inst_i_1
|
||||
(.I0(r1_out[6]),
|
||||
.I1(r0_out[6]),
|
||||
.I2(r3_out[6]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[6]),
|
||||
.O(op0_OBUF[6]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[7]_inst_i_1
|
||||
(.I0(r1_out[7]),
|
||||
.I1(r0_out[7]),
|
||||
.I2(r3_out[7]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[7]),
|
||||
.O(op0_OBUF[7]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[8]_inst_i_1
|
||||
(.I0(r1_out[8]),
|
||||
.I1(r0_out[8]),
|
||||
.I2(r3_out[8]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[8]),
|
||||
.O(op0_OBUF[8]));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "mux_4_1" *)
|
||||
module mux_4_1_0
|
||||
(op1_OBUF,
|
||||
r1_out,
|
||||
r0_out,
|
||||
r3_out,
|
||||
op1_idx_IBUF,
|
||||
r2_out);
|
||||
output [8:0]op1_OBUF;
|
||||
input [8:0]r1_out;
|
||||
input [8:0]r0_out;
|
||||
input [8:0]r3_out;
|
||||
input [1:0]op1_idx_IBUF;
|
||||
input [8:0]r2_out;
|
||||
|
||||
wire [8:0]op1_OBUF;
|
||||
wire [1:0]op1_idx_IBUF;
|
||||
wire [8:0]r0_out;
|
||||
wire [8:0]r1_out;
|
||||
wire [8:0]r2_out;
|
||||
wire [8:0]r3_out;
|
||||
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[0]_inst_i_1
|
||||
(.I0(r1_out[0]),
|
||||
.I1(r0_out[0]),
|
||||
.I2(r3_out[0]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[0]),
|
||||
.O(op1_OBUF[0]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[1]_inst_i_1
|
||||
(.I0(r1_out[1]),
|
||||
.I1(r0_out[1]),
|
||||
.I2(r3_out[1]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[1]),
|
||||
.O(op1_OBUF[1]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[2]_inst_i_1
|
||||
(.I0(r1_out[2]),
|
||||
.I1(r0_out[2]),
|
||||
.I2(r3_out[2]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[2]),
|
||||
.O(op1_OBUF[2]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[3]_inst_i_1
|
||||
(.I0(r1_out[3]),
|
||||
.I1(r0_out[3]),
|
||||
.I2(r3_out[3]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[3]),
|
||||
.O(op1_OBUF[3]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[4]_inst_i_1
|
||||
(.I0(r1_out[4]),
|
||||
.I1(r0_out[4]),
|
||||
.I2(r3_out[4]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[4]),
|
||||
.O(op1_OBUF[4]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[5]_inst_i_1
|
||||
(.I0(r1_out[5]),
|
||||
.I1(r0_out[5]),
|
||||
.I2(r3_out[5]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[5]),
|
||||
.O(op1_OBUF[5]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[6]_inst_i_1
|
||||
(.I0(r1_out[6]),
|
||||
.I1(r0_out[6]),
|
||||
.I2(r3_out[6]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[6]),
|
||||
.O(op1_OBUF[6]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[7]_inst_i_1
|
||||
(.I0(r1_out[7]),
|
||||
.I1(r0_out[7]),
|
||||
.I2(r3_out[7]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[7]),
|
||||
.O(op1_OBUF[7]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[8]_inst_i_1
|
||||
(.I0(r1_out[8]),
|
||||
.I1(r0_out[8]),
|
||||
.I2(r3_out[8]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[8]),
|
||||
.O(op1_OBUF[8]));
|
||||
endmodule
|
||||
|
||||
module register
|
||||
(r0_out,
|
||||
r1_out,
|
||||
r2_out,
|
||||
r3_out,
|
||||
reset_IBUF,
|
||||
write_data_IBUF,
|
||||
clk_IBUF_BUFG,
|
||||
\op0_OBUF[8]_inst_i_1 ,
|
||||
\op0_OBUF[8]_inst_i_1_0 ,
|
||||
\op0_OBUF[8]_inst_i_1_1 ,
|
||||
\op0_OBUF[8]_inst_i_1_2 );
|
||||
output [8:0]r0_out;
|
||||
output [8:0]r1_out;
|
||||
output [8:0]r2_out;
|
||||
output [8:0]r3_out;
|
||||
input reset_IBUF;
|
||||
input [8:0]write_data_IBUF;
|
||||
input clk_IBUF_BUFG;
|
||||
input \op0_OBUF[8]_inst_i_1 ;
|
||||
input \op0_OBUF[8]_inst_i_1_0 ;
|
||||
input \op0_OBUF[8]_inst_i_1_1 ;
|
||||
input \op0_OBUF[8]_inst_i_1_2 ;
|
||||
|
||||
wire \Dout_tristate_oe_reg_n_0_[0] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[1] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[2] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[3] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[4] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[5] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[6] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[7] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[8] ;
|
||||
wire clk_IBUF_BUFG;
|
||||
wire \op0_OBUF[8]_inst_i_1 ;
|
||||
wire \op0_OBUF[8]_inst_i_1_0 ;
|
||||
wire \op0_OBUF[8]_inst_i_1_1 ;
|
||||
wire \op0_OBUF[8]_inst_i_1_2 ;
|
||||
wire [8:0]r0_out;
|
||||
wire [8:0]r1_out;
|
||||
wire [8:0]r2_out;
|
||||
wire [8:0]r3_out;
|
||||
wire reset_IBUF;
|
||||
wire [8:0]write_data_IBUF;
|
||||
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[0]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[0]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[0] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[1]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[1]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[1] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[2]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[2]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[2] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[3]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[3]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[3] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[4]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[4]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[4] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[5]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[5]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[5] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[6]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[6]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[6] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[7]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[7]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[7] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[8]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[8]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[8] ),
|
||||
.R(reset_IBUF));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[0]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[0]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair9" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[0]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair9" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[0]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[1]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[1]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair10" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[1]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair10" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[1]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[2]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[2]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair11" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[2]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair11" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[2]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[3]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[3]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair12" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[3]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair12" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[3]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[4]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[4]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[4]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[4]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair13" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[4]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[4]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair13" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[4]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[4]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[5]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[5]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[5]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[5]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair14" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[5]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[5]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair14" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[5]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[5]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[6]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[6]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[6]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[6]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair15" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[6]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[6]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair15" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[6]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[6]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair7" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[7]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[7]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair7" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[7]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[7]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair16" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[7]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[7]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair16" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[7]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[7]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair8" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[8]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[8]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair8" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[8]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[8]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair17" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[8]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[8]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair17" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[8]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[8]));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
8
lab2CA.sim/sim_1/impl/func/xsim/alu_tb_vlog.prj
Normal file
8
lab2CA.sim/sim_1/impl/func/xsim/alu_tb_vlog.prj
Normal file
@@ -0,0 +1,8 @@
|
||||
# compile verilog/system verilog design source files
|
||||
verilog xil_defaultlib \
|
||||
"alu_tb_func_impl.v" \
|
||||
"../../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
|
||||
"../../../../../lab2CA.srcs/sources_1/new/ALU.v" \
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
12
lab2CA.sim/sim_1/impl/func/xsim/webtalk.jou
Normal file
12
lab2CA.sim/sim_1/impl/func/xsim/webtalk.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sat Feb 16 16:48:49 2019
|
||||
# Process ID: 940
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/webtalk.log
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/webtalk/xsim_webtalk.tcl -notrace
|
||||
BIN
lab2CA.sim/sim_1/impl/func/xsim/xelab.pb
Normal file
BIN
lab2CA.sim/sim_1/impl/func/xsim/xelab.pb
Normal file
Binary file not shown.
@@ -0,0 +1 @@
|
||||
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "alu_tb_func_impl" "xil_defaultlib.alu_tb" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
@@ -0,0 +1,119 @@
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
typedef void (*funcp)(char *, char *);
|
||||
extern int main(int, char**);
|
||||
extern void execute_79(char*, char *);
|
||||
extern void execute_181(char*, char *);
|
||||
extern void execute_182(char*, char *);
|
||||
extern void execute_183(char*, char *);
|
||||
extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
|
||||
extern void execute_180(char*, char *);
|
||||
extern void execute_84(char*, char *);
|
||||
extern void execute_85(char*, char *);
|
||||
extern void execute_129(char*, char *);
|
||||
extern void execute_102(char*, char *);
|
||||
extern void execute_150(char*, char *);
|
||||
extern void execute_159(char*, char *);
|
||||
extern void execute_168(char*, char *);
|
||||
extern void execute_177(char*, char *);
|
||||
extern void execute_178(char*, char *);
|
||||
extern void execute_78(char*, char *);
|
||||
extern void execute_81(char*, char *);
|
||||
extern void execute_82(char*, char *);
|
||||
extern void execute_83(char*, char *);
|
||||
extern void execute_184(char*, char *);
|
||||
extern void execute_185(char*, char *);
|
||||
extern void execute_186(char*, char *);
|
||||
extern void execute_187(char*, char *);
|
||||
extern void execute_188(char*, char *);
|
||||
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
|
||||
funcp funcTab[25] = {(funcp)execute_79, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_180, (funcp)execute_84, (funcp)execute_85, (funcp)execute_129, (funcp)execute_102, (funcp)execute_150, (funcp)execute_159, (funcp)execute_168, (funcp)execute_177, (funcp)execute_178, (funcp)execute_78, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_184, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_188, (funcp)vlog_transfunc_eventcallback};
|
||||
const int NumRelocateId= 25;
|
||||
|
||||
void relocate(char *dp)
|
||||
{
|
||||
iki_relocate(dp, "xsim.dir/alu_tb_func_impl/xsim.reloc", (void **)funcTab, 25);
|
||||
|
||||
/*Populate the transaction function pointer field in the whole net structure */
|
||||
}
|
||||
|
||||
void sensitize(char *dp)
|
||||
{
|
||||
iki_sensitize(dp, "xsim.dir/alu_tb_func_impl/xsim.reloc");
|
||||
}
|
||||
|
||||
void simulate(char *dp)
|
||||
{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/alu_tb_func_impl/xsim.reloc");
|
||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
|
||||
|
||||
// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/alu_tb_func_impl/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/alu_tb_func_impl/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/alu_tb_func_impl/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
@@ -0,0 +1,54 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sat Feb 16 16:48:49 2019'>
|
||||
<section name="__ROOT__" level="0" order="1" description="">
|
||||
<section name="software_version_and_target_device" level="1" order="1" description="">
|
||||
<keyValuePair key="beta" value="FALSE" description="" />
|
||||
<keyValuePair key="build_version" value="2405991" description="" />
|
||||
<keyValuePair key="date_generated" value="Sat Feb 16 16:48:47 2019" description="" />
|
||||
<keyValuePair key="os_platform" value="WIN64" description="" />
|
||||
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
|
||||
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
|
||||
<keyValuePair key="project_iteration" value="1" description="" />
|
||||
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
|
||||
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
|
||||
<keyValuePair key="route_design" value="FALSE" description="" />
|
||||
<keyValuePair key="target_device" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_family" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_package" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_speed" value="not_applicable" description="" />
|
||||
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
|
||||
</section>
|
||||
<section name="user_environment" level="1" order="2" description="">
|
||||
<keyValuePair key="cpu_name" value="Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" description="" />
|
||||
<keyValuePair key="cpu_speed" value="3492 MHz" description="" />
|
||||
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
|
||||
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
|
||||
<keyValuePair key="system_ram" value="34.000 GB" description="" />
|
||||
<keyValuePair key="total_processors" value="1" description="" />
|
||||
</section>
|
||||
<section name="vivado_usage" level="1" order="3" description="">
|
||||
</section>
|
||||
<section name="xsim" level="1" order="4" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="command" value="xelab" description="" />
|
||||
<keyValuePair key="debug" value="typical" description="" />
|
||||
<keyValuePair key="dpi_used" value="false" description="" />
|
||||
<keyValuePair key="file_counter" value="3" description="" />
|
||||
<keyValuePair key="gendll" value="false" description="" />
|
||||
<keyValuePair key="hwcosim" value="false" description="" />
|
||||
<keyValuePair key="sdfmodeling" value="false" description="" />
|
||||
<keyValuePair key="vhdl2008" value="false" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="compiler_memory" value="38692_KB" description="" />
|
||||
<keyValuePair key="compiler_time" value="0.70_sec" description="" />
|
||||
<keyValuePair key="simulation_image_code" value="71 KB" description="" />
|
||||
<keyValuePair key="simulation_image_data" value="8 KB" description="" />
|
||||
<keyValuePair key="total_instances" value="78" description="" />
|
||||
<keyValuePair key="total_nets" value="0" description="" />
|
||||
<keyValuePair key="total_processes" value="113" description="" />
|
||||
<keyValuePair key="xilinx_hdl_libraries_used" value="secureip unisims_ver " description="" />
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</webTalkData>
|
||||
Binary file not shown.
BIN
lab2CA.sim/sim_1/impl/func/xsim/xvlog.pb
Normal file
BIN
lab2CA.sim/sim_1/impl/func/xsim/xvlog.pb
Normal file
Binary file not shown.
11
lab2CA.sim/sim_1/impl/timing/xsim/alu_tb.tcl
Normal file
11
lab2CA.sim/sim_1/impl/timing/xsim/alu_tb.tcl
Normal file
@@ -0,0 +1,11 @@
|
||||
set curr_wave [current_wave_config]
|
||||
if { [string length $curr_wave] == 0 } {
|
||||
if { [llength [get_objects]] > 0} {
|
||||
add_wave /
|
||||
set_property needs_save false [current_wave_config]
|
||||
} else {
|
||||
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
}
|
||||
}
|
||||
|
||||
run 1000ns
|
||||
931
lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_time_impl.v
Normal file
931
lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_time_impl.v
Normal file
@@ -0,0 +1,931 @@
|
||||
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
// Date : Sat Feb 16 16:46:39 2019
|
||||
// Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file
|
||||
// C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_time_impl.v
|
||||
// Design : RegFile
|
||||
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
|
||||
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
|
||||
// Device : xc7k160tifbg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
`define XIL_TIMING
|
||||
|
||||
(* ECO_CHECKSUM = "b4d7812f" *)
|
||||
(* NotValidForBitStream *)
|
||||
module RegFile
|
||||
(clk,
|
||||
reset,
|
||||
write_index,
|
||||
op0_idx,
|
||||
op1_idx,
|
||||
write_data,
|
||||
op0,
|
||||
op1);
|
||||
input clk;
|
||||
input reset;
|
||||
input [1:0]write_index;
|
||||
input [1:0]op0_idx;
|
||||
input [1:0]op1_idx;
|
||||
input [8:0]write_data;
|
||||
output [8:0]op0;
|
||||
output [8:0]op1;
|
||||
|
||||
wire clk;
|
||||
wire clk_IBUF;
|
||||
wire clk_IBUF_BUFG;
|
||||
wire [8:0]op0;
|
||||
wire [8:0]op0_OBUF;
|
||||
wire \op0_OBUF[8]_inst_i_10_n_0 ;
|
||||
wire \op0_OBUF[8]_inst_i_11_n_0 ;
|
||||
wire \op0_OBUF[8]_inst_i_12_n_0 ;
|
||||
wire \op0_OBUF[8]_inst_i_6_n_0 ;
|
||||
wire \op0_OBUF[8]_inst_i_7_n_0 ;
|
||||
wire \op0_OBUF[8]_inst_i_8_n_0 ;
|
||||
wire \op0_OBUF[8]_inst_i_9_n_0 ;
|
||||
wire [1:0]op0_idx;
|
||||
wire [1:0]op0_idx_IBUF;
|
||||
wire [8:0]op1;
|
||||
wire [8:0]op1_OBUF;
|
||||
wire [1:0]op1_idx;
|
||||
wire [1:0]op1_idx_IBUF;
|
||||
wire \r0/_n_0 ;
|
||||
wire [8:0]r0_out;
|
||||
wire [8:0]r1_out;
|
||||
wire [8:0]r2_out;
|
||||
wire [8:0]r3_out;
|
||||
wire reset;
|
||||
wire reset_IBUF;
|
||||
wire [8:0]write_data;
|
||||
wire [8:0]write_data_IBUF;
|
||||
wire [1:0]write_index;
|
||||
wire [1:0]write_index_IBUF;
|
||||
|
||||
initial begin
|
||||
$sdf_annotate("alu_tb_time_impl.sdf",,,,"tool_control");
|
||||
end
|
||||
BUFG clk_IBUF_BUFG_inst
|
||||
(.I(clk_IBUF),
|
||||
.O(clk_IBUF_BUFG));
|
||||
IBUF clk_IBUF_inst
|
||||
(.I(clk),
|
||||
.O(clk_IBUF));
|
||||
mux_4_1 m0
|
||||
(.op0_OBUF(op0_OBUF),
|
||||
.op0_idx_IBUF(op0_idx_IBUF),
|
||||
.r0_out(r0_out),
|
||||
.r1_out(r1_out),
|
||||
.r2_out(r2_out),
|
||||
.r3_out(r3_out));
|
||||
mux_4_1_0 m1
|
||||
(.op1_OBUF(op1_OBUF),
|
||||
.op1_idx_IBUF(op1_idx_IBUF),
|
||||
.r0_out(r0_out),
|
||||
.r1_out(r1_out),
|
||||
.r2_out(r2_out),
|
||||
.r3_out(r3_out));
|
||||
OBUF \op0_OBUF[0]_inst
|
||||
(.I(op0_OBUF[0]),
|
||||
.O(op0[0]));
|
||||
OBUF \op0_OBUF[1]_inst
|
||||
(.I(op0_OBUF[1]),
|
||||
.O(op0[1]));
|
||||
OBUF \op0_OBUF[2]_inst
|
||||
(.I(op0_OBUF[2]),
|
||||
.O(op0[2]));
|
||||
OBUF \op0_OBUF[3]_inst
|
||||
(.I(op0_OBUF[3]),
|
||||
.O(op0[3]));
|
||||
OBUF \op0_OBUF[4]_inst
|
||||
(.I(op0_OBUF[4]),
|
||||
.O(op0[4]));
|
||||
OBUF \op0_OBUF[5]_inst
|
||||
(.I(op0_OBUF[5]),
|
||||
.O(op0[5]));
|
||||
OBUF \op0_OBUF[6]_inst
|
||||
(.I(op0_OBUF[6]),
|
||||
.O(op0[6]));
|
||||
OBUF \op0_OBUF[7]_inst
|
||||
(.I(op0_OBUF[7]),
|
||||
.O(op0[7]));
|
||||
OBUF \op0_OBUF[8]_inst
|
||||
(.I(op0_OBUF[8]),
|
||||
.O(op0[8]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair18" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h4))
|
||||
\op0_OBUF[8]_inst_i_10
|
||||
(.I0(write_index_IBUF[0]),
|
||||
.I1(write_index_IBUF[1]),
|
||||
.O(\op0_OBUF[8]_inst_i_10_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair19" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[8]_inst_i_11
|
||||
(.I0(write_index_IBUF[0]),
|
||||
.I1(write_index_IBUF[1]),
|
||||
.O(\op0_OBUF[8]_inst_i_11_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair19" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h4))
|
||||
\op0_OBUF[8]_inst_i_12
|
||||
(.I0(write_index_IBUF[1]),
|
||||
.I1(write_index_IBUF[0]),
|
||||
.O(\op0_OBUF[8]_inst_i_12_n_0 ));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
\op0_OBUF[8]_inst_i_6
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(\op0_OBUF[8]_inst_i_10_n_0 ),
|
||||
.Q(\op0_OBUF[8]_inst_i_6_n_0 ),
|
||||
.S(reset_IBUF));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
\op0_OBUF[8]_inst_i_7
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(\r0/_n_0 ),
|
||||
.Q(\op0_OBUF[8]_inst_i_7_n_0 ),
|
||||
.S(reset_IBUF));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
\op0_OBUF[8]_inst_i_8
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(\op0_OBUF[8]_inst_i_11_n_0 ),
|
||||
.Q(\op0_OBUF[8]_inst_i_8_n_0 ),
|
||||
.S(reset_IBUF));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
\op0_OBUF[8]_inst_i_9
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(\op0_OBUF[8]_inst_i_12_n_0 ),
|
||||
.Q(\op0_OBUF[8]_inst_i_9_n_0 ),
|
||||
.S(reset_IBUF));
|
||||
IBUF \op0_idx_IBUF[0]_inst
|
||||
(.I(op0_idx[0]),
|
||||
.O(op0_idx_IBUF[0]));
|
||||
IBUF \op0_idx_IBUF[1]_inst
|
||||
(.I(op0_idx[1]),
|
||||
.O(op0_idx_IBUF[1]));
|
||||
OBUF \op1_OBUF[0]_inst
|
||||
(.I(op1_OBUF[0]),
|
||||
.O(op1[0]));
|
||||
OBUF \op1_OBUF[1]_inst
|
||||
(.I(op1_OBUF[1]),
|
||||
.O(op1[1]));
|
||||
OBUF \op1_OBUF[2]_inst
|
||||
(.I(op1_OBUF[2]),
|
||||
.O(op1[2]));
|
||||
OBUF \op1_OBUF[3]_inst
|
||||
(.I(op1_OBUF[3]),
|
||||
.O(op1[3]));
|
||||
OBUF \op1_OBUF[4]_inst
|
||||
(.I(op1_OBUF[4]),
|
||||
.O(op1[4]));
|
||||
OBUF \op1_OBUF[5]_inst
|
||||
(.I(op1_OBUF[5]),
|
||||
.O(op1[5]));
|
||||
OBUF \op1_OBUF[6]_inst
|
||||
(.I(op1_OBUF[6]),
|
||||
.O(op1[6]));
|
||||
OBUF \op1_OBUF[7]_inst
|
||||
(.I(op1_OBUF[7]),
|
||||
.O(op1[7]));
|
||||
OBUF \op1_OBUF[8]_inst
|
||||
(.I(op1_OBUF[8]),
|
||||
.O(op1[8]));
|
||||
IBUF \op1_idx_IBUF[0]_inst
|
||||
(.I(op1_idx[0]),
|
||||
.O(op1_idx_IBUF[0]));
|
||||
IBUF \op1_idx_IBUF[1]_inst
|
||||
(.I(op1_idx[1]),
|
||||
.O(op1_idx_IBUF[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair18" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h1))
|
||||
\r0/
|
||||
(.I0(write_index_IBUF[0]),
|
||||
.I1(write_index_IBUF[1]),
|
||||
.O(\r0/_n_0 ));
|
||||
register r3
|
||||
(.clk_IBUF_BUFG(clk_IBUF_BUFG),
|
||||
.\op0_OBUF[8]_inst_i_1 (\op0_OBUF[8]_inst_i_7_n_0 ),
|
||||
.\op0_OBUF[8]_inst_i_1_0 (\op0_OBUF[8]_inst_i_6_n_0 ),
|
||||
.\op0_OBUF[8]_inst_i_1_1 (\op0_OBUF[8]_inst_i_9_n_0 ),
|
||||
.\op0_OBUF[8]_inst_i_1_2 (\op0_OBUF[8]_inst_i_8_n_0 ),
|
||||
.r0_out(r0_out),
|
||||
.r1_out(r1_out),
|
||||
.r2_out(r2_out),
|
||||
.r3_out(r3_out),
|
||||
.reset_IBUF(reset_IBUF),
|
||||
.write_data_IBUF(write_data_IBUF));
|
||||
IBUF reset_IBUF_inst
|
||||
(.I(reset),
|
||||
.O(reset_IBUF));
|
||||
IBUF \write_data_IBUF[0]_inst
|
||||
(.I(write_data[0]),
|
||||
.O(write_data_IBUF[0]));
|
||||
IBUF \write_data_IBUF[1]_inst
|
||||
(.I(write_data[1]),
|
||||
.O(write_data_IBUF[1]));
|
||||
IBUF \write_data_IBUF[2]_inst
|
||||
(.I(write_data[2]),
|
||||
.O(write_data_IBUF[2]));
|
||||
IBUF \write_data_IBUF[3]_inst
|
||||
(.I(write_data[3]),
|
||||
.O(write_data_IBUF[3]));
|
||||
IBUF \write_data_IBUF[4]_inst
|
||||
(.I(write_data[4]),
|
||||
.O(write_data_IBUF[4]));
|
||||
IBUF \write_data_IBUF[5]_inst
|
||||
(.I(write_data[5]),
|
||||
.O(write_data_IBUF[5]));
|
||||
IBUF \write_data_IBUF[6]_inst
|
||||
(.I(write_data[6]),
|
||||
.O(write_data_IBUF[6]));
|
||||
IBUF \write_data_IBUF[7]_inst
|
||||
(.I(write_data[7]),
|
||||
.O(write_data_IBUF[7]));
|
||||
IBUF \write_data_IBUF[8]_inst
|
||||
(.I(write_data[8]),
|
||||
.O(write_data_IBUF[8]));
|
||||
IBUF \write_index_IBUF[0]_inst
|
||||
(.I(write_index[0]),
|
||||
.O(write_index_IBUF[0]));
|
||||
IBUF \write_index_IBUF[1]_inst
|
||||
(.I(write_index[1]),
|
||||
.O(write_index_IBUF[1]));
|
||||
endmodule
|
||||
|
||||
module mux_4_1
|
||||
(op0_OBUF,
|
||||
r1_out,
|
||||
r0_out,
|
||||
r3_out,
|
||||
op0_idx_IBUF,
|
||||
r2_out);
|
||||
output [8:0]op0_OBUF;
|
||||
input [8:0]r1_out;
|
||||
input [8:0]r0_out;
|
||||
input [8:0]r3_out;
|
||||
input [1:0]op0_idx_IBUF;
|
||||
input [8:0]r2_out;
|
||||
|
||||
wire [8:0]op0_OBUF;
|
||||
wire [1:0]op0_idx_IBUF;
|
||||
wire [8:0]r0_out;
|
||||
wire [8:0]r1_out;
|
||||
wire [8:0]r2_out;
|
||||
wire [8:0]r3_out;
|
||||
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[0]_inst_i_1
|
||||
(.I0(r1_out[0]),
|
||||
.I1(r0_out[0]),
|
||||
.I2(r3_out[0]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[0]),
|
||||
.O(op0_OBUF[0]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[1]_inst_i_1
|
||||
(.I0(r1_out[1]),
|
||||
.I1(r0_out[1]),
|
||||
.I2(r3_out[1]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[1]),
|
||||
.O(op0_OBUF[1]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[2]_inst_i_1
|
||||
(.I0(r1_out[2]),
|
||||
.I1(r0_out[2]),
|
||||
.I2(r3_out[2]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[2]),
|
||||
.O(op0_OBUF[2]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[3]_inst_i_1
|
||||
(.I0(r1_out[3]),
|
||||
.I1(r0_out[3]),
|
||||
.I2(r3_out[3]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[3]),
|
||||
.O(op0_OBUF[3]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[4]_inst_i_1
|
||||
(.I0(r1_out[4]),
|
||||
.I1(r0_out[4]),
|
||||
.I2(r3_out[4]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[4]),
|
||||
.O(op0_OBUF[4]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[5]_inst_i_1
|
||||
(.I0(r1_out[5]),
|
||||
.I1(r0_out[5]),
|
||||
.I2(r3_out[5]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[5]),
|
||||
.O(op0_OBUF[5]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[6]_inst_i_1
|
||||
(.I0(r1_out[6]),
|
||||
.I1(r0_out[6]),
|
||||
.I2(r3_out[6]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[6]),
|
||||
.O(op0_OBUF[6]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[7]_inst_i_1
|
||||
(.I0(r1_out[7]),
|
||||
.I1(r0_out[7]),
|
||||
.I2(r3_out[7]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[7]),
|
||||
.O(op0_OBUF[7]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op0_OBUF[8]_inst_i_1
|
||||
(.I0(r1_out[8]),
|
||||
.I1(r0_out[8]),
|
||||
.I2(r3_out[8]),
|
||||
.I3(op0_idx_IBUF[1]),
|
||||
.I4(op0_idx_IBUF[0]),
|
||||
.I5(r2_out[8]),
|
||||
.O(op0_OBUF[8]));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "mux_4_1" *)
|
||||
module mux_4_1_0
|
||||
(op1_OBUF,
|
||||
r1_out,
|
||||
r0_out,
|
||||
r3_out,
|
||||
op1_idx_IBUF,
|
||||
r2_out);
|
||||
output [8:0]op1_OBUF;
|
||||
input [8:0]r1_out;
|
||||
input [8:0]r0_out;
|
||||
input [8:0]r3_out;
|
||||
input [1:0]op1_idx_IBUF;
|
||||
input [8:0]r2_out;
|
||||
|
||||
wire [8:0]op1_OBUF;
|
||||
wire [1:0]op1_idx_IBUF;
|
||||
wire [8:0]r0_out;
|
||||
wire [8:0]r1_out;
|
||||
wire [8:0]r2_out;
|
||||
wire [8:0]r3_out;
|
||||
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[0]_inst_i_1
|
||||
(.I0(r1_out[0]),
|
||||
.I1(r0_out[0]),
|
||||
.I2(r3_out[0]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[0]),
|
||||
.O(op1_OBUF[0]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[1]_inst_i_1
|
||||
(.I0(r1_out[1]),
|
||||
.I1(r0_out[1]),
|
||||
.I2(r3_out[1]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[1]),
|
||||
.O(op1_OBUF[1]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[2]_inst_i_1
|
||||
(.I0(r1_out[2]),
|
||||
.I1(r0_out[2]),
|
||||
.I2(r3_out[2]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[2]),
|
||||
.O(op1_OBUF[2]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[3]_inst_i_1
|
||||
(.I0(r1_out[3]),
|
||||
.I1(r0_out[3]),
|
||||
.I2(r3_out[3]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[3]),
|
||||
.O(op1_OBUF[3]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[4]_inst_i_1
|
||||
(.I0(r1_out[4]),
|
||||
.I1(r0_out[4]),
|
||||
.I2(r3_out[4]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[4]),
|
||||
.O(op1_OBUF[4]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[5]_inst_i_1
|
||||
(.I0(r1_out[5]),
|
||||
.I1(r0_out[5]),
|
||||
.I2(r3_out[5]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[5]),
|
||||
.O(op1_OBUF[5]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[6]_inst_i_1
|
||||
(.I0(r1_out[6]),
|
||||
.I1(r0_out[6]),
|
||||
.I2(r3_out[6]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[6]),
|
||||
.O(op1_OBUF[6]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[7]_inst_i_1
|
||||
(.I0(r1_out[7]),
|
||||
.I1(r0_out[7]),
|
||||
.I2(r3_out[7]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[7]),
|
||||
.O(op1_OBUF[7]));
|
||||
LUT6 #(
|
||||
.INIT(64'hF0AAFFCCF0AA00CC))
|
||||
\op1_OBUF[8]_inst_i_1
|
||||
(.I0(r1_out[8]),
|
||||
.I1(r0_out[8]),
|
||||
.I2(r3_out[8]),
|
||||
.I3(op1_idx_IBUF[1]),
|
||||
.I4(op1_idx_IBUF[0]),
|
||||
.I5(r2_out[8]),
|
||||
.O(op1_OBUF[8]));
|
||||
endmodule
|
||||
|
||||
module register
|
||||
(r0_out,
|
||||
r1_out,
|
||||
r2_out,
|
||||
r3_out,
|
||||
reset_IBUF,
|
||||
write_data_IBUF,
|
||||
clk_IBUF_BUFG,
|
||||
\op0_OBUF[8]_inst_i_1 ,
|
||||
\op0_OBUF[8]_inst_i_1_0 ,
|
||||
\op0_OBUF[8]_inst_i_1_1 ,
|
||||
\op0_OBUF[8]_inst_i_1_2 );
|
||||
output [8:0]r0_out;
|
||||
output [8:0]r1_out;
|
||||
output [8:0]r2_out;
|
||||
output [8:0]r3_out;
|
||||
input reset_IBUF;
|
||||
input [8:0]write_data_IBUF;
|
||||
input clk_IBUF_BUFG;
|
||||
input \op0_OBUF[8]_inst_i_1 ;
|
||||
input \op0_OBUF[8]_inst_i_1_0 ;
|
||||
input \op0_OBUF[8]_inst_i_1_1 ;
|
||||
input \op0_OBUF[8]_inst_i_1_2 ;
|
||||
|
||||
wire \Dout_tristate_oe_reg_n_0_[0] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[1] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[2] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[3] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[4] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[5] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[6] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[7] ;
|
||||
wire \Dout_tristate_oe_reg_n_0_[8] ;
|
||||
wire clk_IBUF_BUFG;
|
||||
wire \op0_OBUF[8]_inst_i_1 ;
|
||||
wire \op0_OBUF[8]_inst_i_1_0 ;
|
||||
wire \op0_OBUF[8]_inst_i_1_1 ;
|
||||
wire \op0_OBUF[8]_inst_i_1_2 ;
|
||||
wire [8:0]r0_out;
|
||||
wire [8:0]r1_out;
|
||||
wire [8:0]r2_out;
|
||||
wire [8:0]r3_out;
|
||||
wire reset_IBUF;
|
||||
wire [8:0]write_data_IBUF;
|
||||
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[0]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[0]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[0] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[1]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[1]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[1] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[2]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[2]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[2] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[3]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[3]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[3] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[4]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[4]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[4] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[5]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[5]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[5] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[6]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[6]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[6] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[7]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[7]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[7] ),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_tristate_oe_reg[8]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(write_data_IBUF[8]),
|
||||
.Q(\Dout_tristate_oe_reg_n_0_[8] ),
|
||||
.R(reset_IBUF));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[0]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[0]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair9" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[0]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair9" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[0]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[1]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[1]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair10" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[1]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair10" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[1]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[2]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[2]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair11" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[2]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair11" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[2]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[3]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[3]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair12" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[3]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair12" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[3]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[4]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[4]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[4]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[4]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair13" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[4]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[4]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair13" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[4]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[4]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[5]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[5]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[5]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[5]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair14" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[5]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[5]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair14" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[5]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[5]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[6]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[6]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[6]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[6]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair15" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[6]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[6]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair15" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[6]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[6]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair7" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[7]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[7]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair7" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[7]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[7]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair16" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[7]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[7]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair16" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[7]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[7]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair8" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[8]_inst_i_2
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_0 ),
|
||||
.O(r1_out[8]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair8" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[8]_inst_i_3
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1 ),
|
||||
.O(r0_out[8]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair17" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[8]_inst_i_4
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_2 ),
|
||||
.O(r3_out[8]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair17" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\op0_OBUF[8]_inst_i_5
|
||||
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
|
||||
.I1(\op0_OBUF[8]_inst_i_1_1 ),
|
||||
.O(r2_out[8]));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
8
lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_vlog.prj
Normal file
8
lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_vlog.prj
Normal file
@@ -0,0 +1,8 @@
|
||||
# compile verilog/system verilog design source files
|
||||
verilog xil_defaultlib \
|
||||
"alu_tb_time_impl.v" \
|
||||
"../../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
|
||||
"../../../../../lab2CA.srcs/sources_1/new/ALU.v" \
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
11
lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb.tcl
Normal file
11
lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb.tcl
Normal file
@@ -0,0 +1,11 @@
|
||||
set curr_wave [current_wave_config]
|
||||
if { [string length $curr_wave] == 0 } {
|
||||
if { [llength [get_objects]] > 0} {
|
||||
add_wave /
|
||||
set_property needs_save false [current_wave_config]
|
||||
} else {
|
||||
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
}
|
||||
}
|
||||
|
||||
run 1000ns
|
||||
463
lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_time_impl.v
Normal file
463
lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_time_impl.v
Normal file
@@ -0,0 +1,463 @@
|
||||
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
// Date : Sat Feb 16 17:29:30 2019
|
||||
// Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file
|
||||
// C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_time_impl.v
|
||||
// Design : FetchUnit
|
||||
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
|
||||
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
|
||||
// Device : xc7k160tifbg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
`define XIL_TIMING
|
||||
|
||||
(* ECO_CHECKSUM = "fb52d5c" *)
|
||||
(* NotValidForBitStream *)
|
||||
module FetchUnit
|
||||
(clk,
|
||||
reset,
|
||||
op_idx,
|
||||
AddrIn,
|
||||
AddrOut);
|
||||
input clk;
|
||||
input reset;
|
||||
input op_idx;
|
||||
input [8:0]AddrIn;
|
||||
output [8:0]AddrOut;
|
||||
|
||||
wire [8:0]AddrIn;
|
||||
wire [8:0]AddrIn_IBUF;
|
||||
wire [8:0]AddrOut;
|
||||
wire [8:0]AddrOut_OBUF;
|
||||
wire clk;
|
||||
wire clk_IBUF;
|
||||
wire clk_IBUF_BUFG;
|
||||
wire op_idx;
|
||||
wire op_idx_IBUF;
|
||||
wire reset;
|
||||
wire reset_IBUF;
|
||||
|
||||
initial begin
|
||||
$sdf_annotate("regFile_tb_time_impl.sdf",,,,"tool_control");
|
||||
end
|
||||
IBUF \AddrIn_IBUF[0]_inst
|
||||
(.I(AddrIn[0]),
|
||||
.O(AddrIn_IBUF[0]));
|
||||
IBUF \AddrIn_IBUF[1]_inst
|
||||
(.I(AddrIn[1]),
|
||||
.O(AddrIn_IBUF[1]));
|
||||
IBUF \AddrIn_IBUF[2]_inst
|
||||
(.I(AddrIn[2]),
|
||||
.O(AddrIn_IBUF[2]));
|
||||
IBUF \AddrIn_IBUF[3]_inst
|
||||
(.I(AddrIn[3]),
|
||||
.O(AddrIn_IBUF[3]));
|
||||
IBUF \AddrIn_IBUF[4]_inst
|
||||
(.I(AddrIn[4]),
|
||||
.O(AddrIn_IBUF[4]));
|
||||
IBUF \AddrIn_IBUF[5]_inst
|
||||
(.I(AddrIn[5]),
|
||||
.O(AddrIn_IBUF[5]));
|
||||
IBUF \AddrIn_IBUF[6]_inst
|
||||
(.I(AddrIn[6]),
|
||||
.O(AddrIn_IBUF[6]));
|
||||
IBUF \AddrIn_IBUF[7]_inst
|
||||
(.I(AddrIn[7]),
|
||||
.O(AddrIn_IBUF[7]));
|
||||
IBUF \AddrIn_IBUF[8]_inst
|
||||
(.I(AddrIn[8]),
|
||||
.O(AddrIn_IBUF[8]));
|
||||
OBUF \AddrOut_OBUF[0]_inst
|
||||
(.I(AddrOut_OBUF[0]),
|
||||
.O(AddrOut[0]));
|
||||
OBUF \AddrOut_OBUF[1]_inst
|
||||
(.I(AddrOut_OBUF[1]),
|
||||
.O(AddrOut[1]));
|
||||
OBUF \AddrOut_OBUF[2]_inst
|
||||
(.I(AddrOut_OBUF[2]),
|
||||
.O(AddrOut[2]));
|
||||
OBUF \AddrOut_OBUF[3]_inst
|
||||
(.I(AddrOut_OBUF[3]),
|
||||
.O(AddrOut[3]));
|
||||
OBUF \AddrOut_OBUF[4]_inst
|
||||
(.I(AddrOut_OBUF[4]),
|
||||
.O(AddrOut[4]));
|
||||
OBUF \AddrOut_OBUF[5]_inst
|
||||
(.I(AddrOut_OBUF[5]),
|
||||
.O(AddrOut[5]));
|
||||
OBUF \AddrOut_OBUF[6]_inst
|
||||
(.I(AddrOut_OBUF[6]),
|
||||
.O(AddrOut[6]));
|
||||
OBUF \AddrOut_OBUF[7]_inst
|
||||
(.I(AddrOut_OBUF[7]),
|
||||
.O(AddrOut[7]));
|
||||
OBUF \AddrOut_OBUF[8]_inst
|
||||
(.I(AddrOut_OBUF[8]),
|
||||
.O(AddrOut[8]));
|
||||
register PC
|
||||
(.AddrIn_IBUF(AddrIn_IBUF),
|
||||
.AddrOut_OBUF(AddrOut_OBUF),
|
||||
.clk_IBUF_BUFG(clk_IBUF_BUFG),
|
||||
.op_idx_IBUF(op_idx_IBUF),
|
||||
.reset_IBUF(reset_IBUF));
|
||||
BUFG clk_IBUF_BUFG_inst
|
||||
(.I(clk_IBUF),
|
||||
.O(clk_IBUF_BUFG));
|
||||
IBUF clk_IBUF_inst
|
||||
(.I(clk),
|
||||
.O(clk_IBUF));
|
||||
IBUF op_idx_IBUF_inst
|
||||
(.I(op_idx),
|
||||
.O(op_idx_IBUF));
|
||||
IBUF reset_IBUF_inst
|
||||
(.I(reset),
|
||||
.O(reset_IBUF));
|
||||
endmodule
|
||||
|
||||
module register
|
||||
(AddrOut_OBUF,
|
||||
reset_IBUF,
|
||||
clk_IBUF_BUFG,
|
||||
op_idx_IBUF,
|
||||
AddrIn_IBUF);
|
||||
output [8:0]AddrOut_OBUF;
|
||||
input reset_IBUF;
|
||||
input clk_IBUF_BUFG;
|
||||
input op_idx_IBUF;
|
||||
input [8:0]AddrIn_IBUF;
|
||||
|
||||
wire [8:0]AddrIn_IBUF;
|
||||
wire [8:0]AddrOut_OBUF;
|
||||
wire \AddrOut_OBUF[8]_inst_i_2_n_0 ;
|
||||
wire \Dout[8]_i_2_n_0 ;
|
||||
wire clk_IBUF_BUFG;
|
||||
wire op_idx_IBUF;
|
||||
wire [8:0]out;
|
||||
wire [8:0]progC_out;
|
||||
wire reset_IBUF;
|
||||
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\AddrOut_OBUF[0]_inst_i_1
|
||||
(.I0(progC_out[0]),
|
||||
.O(AddrOut_OBUF[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\AddrOut_OBUF[1]_inst_i_1
|
||||
(.I0(progC_out[0]),
|
||||
.I1(progC_out[1]),
|
||||
.O(AddrOut_OBUF[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h6A))
|
||||
\AddrOut_OBUF[2]_inst_i_1
|
||||
(.I0(progC_out[2]),
|
||||
.I1(progC_out[0]),
|
||||
.I2(progC_out[1]),
|
||||
.O(AddrOut_OBUF[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h7F80))
|
||||
\AddrOut_OBUF[3]_inst_i_1
|
||||
(.I0(progC_out[1]),
|
||||
.I1(progC_out[0]),
|
||||
.I2(progC_out[2]),
|
||||
.I3(progC_out[3]),
|
||||
.O(AddrOut_OBUF[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h6AAAAAAA))
|
||||
\AddrOut_OBUF[4]_inst_i_1
|
||||
(.I0(progC_out[4]),
|
||||
.I1(progC_out[1]),
|
||||
.I2(progC_out[0]),
|
||||
.I3(progC_out[2]),
|
||||
.I4(progC_out[3]),
|
||||
.O(AddrOut_OBUF[4]));
|
||||
LUT6 #(
|
||||
.INIT(64'h6AAAAAAAAAAAAAAA))
|
||||
\AddrOut_OBUF[5]_inst_i_1
|
||||
(.I0(progC_out[5]),
|
||||
.I1(progC_out[3]),
|
||||
.I2(progC_out[2]),
|
||||
.I3(progC_out[0]),
|
||||
.I4(progC_out[1]),
|
||||
.I5(progC_out[4]),
|
||||
.O(AddrOut_OBUF[5]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h6AAA))
|
||||
\AddrOut_OBUF[6]_inst_i_1
|
||||
(.I0(progC_out[6]),
|
||||
.I1(progC_out[4]),
|
||||
.I2(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
|
||||
.I3(progC_out[5]),
|
||||
.O(AddrOut_OBUF[6]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h6AAAAAAA))
|
||||
\AddrOut_OBUF[7]_inst_i_1
|
||||
(.I0(progC_out[7]),
|
||||
.I1(progC_out[5]),
|
||||
.I2(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
|
||||
.I3(progC_out[4]),
|
||||
.I4(progC_out[6]),
|
||||
.O(AddrOut_OBUF[7]));
|
||||
LUT6 #(
|
||||
.INIT(64'h6AAAAAAAAAAAAAAA))
|
||||
\AddrOut_OBUF[8]_inst_i_1
|
||||
(.I0(progC_out[8]),
|
||||
.I1(progC_out[6]),
|
||||
.I2(progC_out[4]),
|
||||
.I3(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
|
||||
.I4(progC_out[5]),
|
||||
.I5(progC_out[7]),
|
||||
.O(AddrOut_OBUF[8]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h8000))
|
||||
\AddrOut_OBUF[8]_inst_i_2
|
||||
(.I0(progC_out[3]),
|
||||
.I1(progC_out[2]),
|
||||
.I2(progC_out[0]),
|
||||
.I3(progC_out[1]),
|
||||
.O(\AddrOut_OBUF[8]_inst_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h74))
|
||||
\Dout[0]_i_1
|
||||
(.I0(progC_out[0]),
|
||||
.I1(op_idx_IBUF),
|
||||
.I2(AddrIn_IBUF[0]),
|
||||
.O(out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h6F60))
|
||||
\Dout[1]_i_1
|
||||
(.I0(progC_out[0]),
|
||||
.I1(progC_out[1]),
|
||||
.I2(op_idx_IBUF),
|
||||
.I3(AddrIn_IBUF[1]),
|
||||
.O(out[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h6AFF6A00))
|
||||
\Dout[2]_i_1
|
||||
(.I0(progC_out[2]),
|
||||
.I1(progC_out[0]),
|
||||
.I2(progC_out[1]),
|
||||
.I3(op_idx_IBUF),
|
||||
.I4(AddrIn_IBUF[2]),
|
||||
.O(out[2]));
|
||||
LUT6 #(
|
||||
.INIT(64'h7F80FFFF7F800000))
|
||||
\Dout[3]_i_1
|
||||
(.I0(progC_out[1]),
|
||||
.I1(progC_out[0]),
|
||||
.I2(progC_out[2]),
|
||||
.I3(progC_out[3]),
|
||||
.I4(op_idx_IBUF),
|
||||
.I5(AddrIn_IBUF[3]),
|
||||
.O(out[3]));
|
||||
LUT4 #(
|
||||
.INIT(16'h6F60))
|
||||
\Dout[4]_i_1
|
||||
(.I0(progC_out[4]),
|
||||
.I1(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
|
||||
.I2(op_idx_IBUF),
|
||||
.I3(AddrIn_IBUF[4]),
|
||||
.O(out[4]));
|
||||
LUT5 #(
|
||||
.INIT(32'h6AFF6A00))
|
||||
\Dout[5]_i_1
|
||||
(.I0(progC_out[5]),
|
||||
.I1(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
|
||||
.I2(progC_out[4]),
|
||||
.I3(op_idx_IBUF),
|
||||
.I4(AddrIn_IBUF[5]),
|
||||
.O(out[5]));
|
||||
LUT6 #(
|
||||
.INIT(64'h6AAAFFFF6AAA0000))
|
||||
\Dout[6]_i_1
|
||||
(.I0(progC_out[6]),
|
||||
.I1(progC_out[4]),
|
||||
.I2(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
|
||||
.I3(progC_out[5]),
|
||||
.I4(op_idx_IBUF),
|
||||
.I5(AddrIn_IBUF[6]),
|
||||
.O(out[6]));
|
||||
LUT5 #(
|
||||
.INIT(32'h6AFF6A00))
|
||||
\Dout[7]_i_1
|
||||
(.I0(progC_out[7]),
|
||||
.I1(\Dout[8]_i_2_n_0 ),
|
||||
.I2(progC_out[6]),
|
||||
.I3(op_idx_IBUF),
|
||||
.I4(AddrIn_IBUF[7]),
|
||||
.O(out[7]));
|
||||
LUT6 #(
|
||||
.INIT(64'h6AAAFFFF6AAA0000))
|
||||
\Dout[8]_i_1
|
||||
(.I0(progC_out[8]),
|
||||
.I1(progC_out[6]),
|
||||
.I2(\Dout[8]_i_2_n_0 ),
|
||||
.I3(progC_out[7]),
|
||||
.I4(op_idx_IBUF),
|
||||
.I5(AddrIn_IBUF[8]),
|
||||
.O(out[8]));
|
||||
LUT6 #(
|
||||
.INIT(64'h8000000000000000))
|
||||
\Dout[8]_i_2
|
||||
(.I0(progC_out[5]),
|
||||
.I1(progC_out[3]),
|
||||
.I2(progC_out[2]),
|
||||
.I3(progC_out[0]),
|
||||
.I4(progC_out[1]),
|
||||
.I5(progC_out[4]),
|
||||
.O(\Dout[8]_i_2_n_0 ));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_reg[0]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(out[0]),
|
||||
.Q(progC_out[0]),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_reg[1]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(out[1]),
|
||||
.Q(progC_out[1]),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_reg[2]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(out[2]),
|
||||
.Q(progC_out[2]),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_reg[3]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(out[3]),
|
||||
.Q(progC_out[3]),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_reg[4]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(out[4]),
|
||||
.Q(progC_out[4]),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_reg[5]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(out[5]),
|
||||
.Q(progC_out[5]),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_reg[6]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(out[6]),
|
||||
.Q(progC_out[6]),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_reg[7]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(out[7]),
|
||||
.Q(progC_out[7]),
|
||||
.R(reset_IBUF));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\Dout_reg[8]
|
||||
(.C(clk_IBUF_BUFG),
|
||||
.CE(1'b1),
|
||||
.D(out[8]),
|
||||
.Q(progC_out[8]),
|
||||
.R(reset_IBUF));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
8
lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_vlog.prj
Normal file
8
lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_vlog.prj
Normal file
@@ -0,0 +1,8 @@
|
||||
# compile verilog/system verilog design source files
|
||||
verilog xil_defaultlib \
|
||||
"regFile_tb_time_impl.v" \
|
||||
"../../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
|
||||
"../../../../../lab2CA.srcs/sources_1/new/RegFile.v" \
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
@@ -2,11 +2,11 @@
|
||||
# Webtalk v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Fri Feb 15 12:37:49 2019
|
||||
# Process ID: 17624
|
||||
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log
|
||||
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou
|
||||
# Start of session at: Sat Feb 16 17:29:42 2019
|
||||
# Process ID: 9128
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/regFile_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source C:/Users/JoseIgnacio/CA -notrace
|
||||
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/regFile_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace
|
||||
|
||||
12
lab2CA.sim/sim_1/impl/timing/xsim/webtalk_12684.backup.jou
Normal file
12
lab2CA.sim/sim_1/impl/timing/xsim/webtalk_12684.backup.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sat Feb 16 16:46:35 2019
|
||||
# Process ID: 12684
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace
|
||||
12
lab2CA.sim/sim_1/impl/timing/xsim/webtalk_17624.backup.jou
Normal file
12
lab2CA.sim/sim_1/impl/timing/xsim/webtalk_17624.backup.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Fri Feb 15 12:37:49 2019
|
||||
# Process ID: 17624
|
||||
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log
|
||||
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source C:/Users/JoseIgnacio/CA -notrace
|
||||
12
lab2CA.sim/sim_1/impl/timing/xsim/webtalk_6004.backup.jou
Normal file
12
lab2CA.sim/sim_1/impl/timing/xsim/webtalk_6004.backup.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sat Feb 16 16:44:18 2019
|
||||
# Process ID: 6004
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/xsim_webtalk.tcl -notrace
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" --maxdelay -L "xil_defaultlib" -L "simprims_ver" -L "secureip" --snapshot "alu_tb_time_impl" -transport_int_delays -pulse_r "0" -pulse_int_r "0" -pulse_e "0" -pulse_int_e "0" "xil_defaultlib.alu_tb" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
@@ -0,0 +1,119 @@
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
typedef void (*funcp)(char *, char *);
|
||||
extern int main(int, char**);
|
||||
extern void execute_79(char*, char *);
|
||||
extern void execute_181(char*, char *);
|
||||
extern void execute_182(char*, char *);
|
||||
extern void execute_183(char*, char *);
|
||||
extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
|
||||
extern void execute_180(char*, char *);
|
||||
extern void execute_84(char*, char *);
|
||||
extern void execute_85(char*, char *);
|
||||
extern void execute_129(char*, char *);
|
||||
extern void execute_102(char*, char *);
|
||||
extern void execute_150(char*, char *);
|
||||
extern void execute_159(char*, char *);
|
||||
extern void execute_168(char*, char *);
|
||||
extern void execute_177(char*, char *);
|
||||
extern void execute_178(char*, char *);
|
||||
extern void execute_78(char*, char *);
|
||||
extern void execute_81(char*, char *);
|
||||
extern void execute_82(char*, char *);
|
||||
extern void execute_83(char*, char *);
|
||||
extern void execute_184(char*, char *);
|
||||
extern void execute_185(char*, char *);
|
||||
extern void execute_186(char*, char *);
|
||||
extern void execute_187(char*, char *);
|
||||
extern void execute_188(char*, char *);
|
||||
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
|
||||
funcp funcTab[25] = {(funcp)execute_79, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_180, (funcp)execute_84, (funcp)execute_85, (funcp)execute_129, (funcp)execute_102, (funcp)execute_150, (funcp)execute_159, (funcp)execute_168, (funcp)execute_177, (funcp)execute_178, (funcp)execute_78, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_184, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_188, (funcp)vlog_transfunc_eventcallback};
|
||||
const int NumRelocateId= 25;
|
||||
|
||||
void relocate(char *dp)
|
||||
{
|
||||
iki_relocate(dp, "xsim.dir/alu_tb_time_impl/xsim.reloc", (void **)funcTab, 25);
|
||||
|
||||
/*Populate the transaction function pointer field in the whole net structure */
|
||||
}
|
||||
|
||||
void sensitize(char *dp)
|
||||
{
|
||||
iki_sensitize(dp, "xsim.dir/alu_tb_time_impl/xsim.reloc");
|
||||
}
|
||||
|
||||
void simulate(char *dp)
|
||||
{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/alu_tb_time_impl/xsim.reloc");
|
||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
|
||||
|
||||
// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/alu_tb_time_impl/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/alu_tb_time_impl/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/alu_tb_time_impl/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sat Feb 16 16:46:35 2019'>
|
||||
<section name="__ROOT__" level="0" order="1" description="">
|
||||
<section name="software_version_and_target_device" level="1" order="1" description="">
|
||||
<keyValuePair key="beta" value="FALSE" description="" />
|
||||
<keyValuePair key="build_version" value="2405991" description="" />
|
||||
<keyValuePair key="date_generated" value="Sat Feb 16 16:46:34 2019" description="" />
|
||||
<keyValuePair key="os_platform" value="WIN64" description="" />
|
||||
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
|
||||
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
|
||||
<keyValuePair key="project_iteration" value="2" description="" />
|
||||
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
|
||||
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
|
||||
<keyValuePair key="route_design" value="FALSE" description="" />
|
||||
<keyValuePair key="target_device" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_family" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_package" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_speed" value="not_applicable" description="" />
|
||||
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
|
||||
</section>
|
||||
<section name="user_environment" level="1" order="2" description="">
|
||||
<keyValuePair key="cpu_name" value="Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" description="" />
|
||||
<keyValuePair key="cpu_speed" value="3492 MHz" description="" />
|
||||
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
|
||||
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
|
||||
<keyValuePair key="system_ram" value="34.000 GB" description="" />
|
||||
<keyValuePair key="total_processors" value="1" description="" />
|
||||
</section>
|
||||
<section name="vivado_usage" level="1" order="3" description="">
|
||||
</section>
|
||||
<section name="xsim" level="1" order="4" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="command" value="xsim" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="iteration" value="0" description="" />
|
||||
<keyValuePair key="runtime" value="40 ns" description="" />
|
||||
<keyValuePair key="simulation_memory" value="6708_KB" description="" />
|
||||
<keyValuePair key="simulation_time" value="0.03_sec" description="" />
|
||||
<keyValuePair key="trace_waveform" value="true" description="" />
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</webTalkData>
|
||||
@@ -0,0 +1,42 @@
|
||||
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/
|
||||
webtalk_register_client -client project
|
||||
webtalk_add_data -client project -key date_generated -value "Sat Feb 16 16:46:45 2019" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key project_iteration -value "3" -context "software_version_and_target_device"
|
||||
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
|
||||
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment"
|
||||
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
|
||||
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
|
||||
webtalk_register_client -client xsim
|
||||
webtalk_add_data -client xsim -key File_Counter -value "3" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
|
||||
webtalk_add_data -client xsim -key Simulation_Image_Code -value "71 KB" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Simulation_Image_Data -value "8 KB" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Processes -value "113" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Total_Instances -value "78" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip simprims_ver " -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Compiler_Time -value "0.69_sec" -context "xsim\\usage"
|
||||
webtalk_add_data -client xsim -key Compiler_Memory -value "38776_KB" -context "xsim\\usage"
|
||||
webtalk_transmit -clientid 1649025917 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/alu_tb_time_impl/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
|
||||
webtalk_terminate
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" --maxdelay -L "xil_defaultlib" -L "simprims_ver" -L "secureip" --snapshot "regFile_tb_time_impl" -transport_int_delays -pulse_r "0" -pulse_int_r "0" -pulse_e "0" -pulse_int_e "0" "xil_defaultlib.regFile_tb" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
@@ -0,0 +1,124 @@
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
|
||||
|
||||
|
||||
#include "iki.h"
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
typedef void (*funcp)(char *, char *);
|
||||
extern int main(int, char**);
|
||||
extern void execute_2(char*, char *);
|
||||
extern void execute_3(char*, char *);
|
||||
extern void execute_17(char*, char *);
|
||||
extern void execute_31(char*, char *);
|
||||
extern void execute_32(char*, char *);
|
||||
extern void execute_33(char*, char *);
|
||||
extern void execute_34(char*, char *);
|
||||
extern void execute_35(char*, char *);
|
||||
extern void execute_36(char*, char *);
|
||||
extern void execute_22(char*, char *);
|
||||
extern void execute_23(char*, char *);
|
||||
extern void execute_24(char*, char *);
|
||||
extern void execute_25(char*, char *);
|
||||
extern void execute_26(char*, char *);
|
||||
extern void execute_27(char*, char *);
|
||||
extern void execute_28(char*, char *);
|
||||
extern void execute_29(char*, char *);
|
||||
extern void execute_30(char*, char *);
|
||||
extern void execute_6(char*, char *);
|
||||
extern void execute_14(char*, char *);
|
||||
extern void execute_19(char*, char *);
|
||||
extern void execute_20(char*, char *);
|
||||
extern void execute_21(char*, char *);
|
||||
extern void execute_37(char*, char *);
|
||||
extern void execute_38(char*, char *);
|
||||
extern void execute_39(char*, char *);
|
||||
extern void execute_40(char*, char *);
|
||||
extern void execute_41(char*, char *);
|
||||
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
|
||||
extern void transaction_10(char*, char*, unsigned, unsigned, unsigned);
|
||||
funcp funcTab[30] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_17, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_6, (funcp)execute_14, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_10};
|
||||
const int NumRelocateId= 30;
|
||||
|
||||
void relocate(char *dp)
|
||||
{
|
||||
iki_relocate(dp, "xsim.dir/regFile_tb_time_impl/xsim.reloc", (void **)funcTab, 30);
|
||||
|
||||
/*Populate the transaction function pointer field in the whole net structure */
|
||||
}
|
||||
|
||||
void sensitize(char *dp)
|
||||
{
|
||||
iki_sensitize(dp, "xsim.dir/regFile_tb_time_impl/xsim.reloc");
|
||||
}
|
||||
|
||||
void simulate(char *dp)
|
||||
{
|
||||
iki_schedule_processes_at_time_zero(dp, "xsim.dir/regFile_tb_time_impl/xsim.reloc");
|
||||
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
|
||||
iki_execute_processes();
|
||||
|
||||
// Schedule resolution functions for the multiply driven Verilog nets that have strength
|
||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
|
||||
|
||||
}
|
||||
#include "iki_bridge.h"
|
||||
void relocate(char *);
|
||||
|
||||
void sensitize(char *);
|
||||
|
||||
void simulate(char *);
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
|
||||
extern void implicit_HDL_SCinstatiate();
|
||||
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
|
||||
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
|
||||
iki_set_sv_type_file_path_name("xsim.dir/regFile_tb_time_impl/xsim.svtype");
|
||||
iki_set_crvs_dump_file_path_name("xsim.dir/regFile_tb_time_impl/xsim.crvsdump");
|
||||
void* design_handle = iki_create_design("xsim.dir/regFile_tb_time_impl/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
|
||||
iki_set_rc_trial_count(100);
|
||||
(void) design_handle;
|
||||
return iki_simulate_design();
|
||||
}
|
||||
@@ -0,0 +1,54 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sat Feb 16 17:29:42 2019'>
|
||||
<section name="__ROOT__" level="0" order="1" description="">
|
||||
<section name="software_version_and_target_device" level="1" order="1" description="">
|
||||
<keyValuePair key="beta" value="FALSE" description="" />
|
||||
<keyValuePair key="build_version" value="2405991" description="" />
|
||||
<keyValuePair key="date_generated" value="Sat Feb 16 17:29:41 2019" description="" />
|
||||
<keyValuePair key="os_platform" value="WIN64" description="" />
|
||||
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
|
||||
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
|
||||
<keyValuePair key="project_iteration" value="1" description="" />
|
||||
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
|
||||
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
|
||||
<keyValuePair key="route_design" value="FALSE" description="" />
|
||||
<keyValuePair key="target_device" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_family" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_package" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_speed" value="not_applicable" description="" />
|
||||
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
|
||||
</section>
|
||||
<section name="user_environment" level="1" order="2" description="">
|
||||
<keyValuePair key="cpu_name" value="Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" description="" />
|
||||
<keyValuePair key="cpu_speed" value="3492 MHz" description="" />
|
||||
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
|
||||
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
|
||||
<keyValuePair key="system_ram" value="34.000 GB" description="" />
|
||||
<keyValuePair key="total_processors" value="1" description="" />
|
||||
</section>
|
||||
<section name="vivado_usage" level="1" order="3" description="">
|
||||
</section>
|
||||
<section name="xsim" level="1" order="4" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="command" value="xelab" description="" />
|
||||
<keyValuePair key="debug" value="typical" description="" />
|
||||
<keyValuePair key="dpi_used" value="false" description="" />
|
||||
<keyValuePair key="file_counter" value="3" description="" />
|
||||
<keyValuePair key="gendll" value="false" description="" />
|
||||
<keyValuePair key="hwcosim" value="false" description="" />
|
||||
<keyValuePair key="sdfmodeling" value="false" description="" />
|
||||
<keyValuePair key="vhdl2008" value="false" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="compiler_memory" value="38640_KB" description="" />
|
||||
<keyValuePair key="compiler_time" value="0.70_sec" description="" />
|
||||
<keyValuePair key="simulation_image_code" value="72 KB" description="" />
|
||||
<keyValuePair key="simulation_image_data" value="4 KB" description="" />
|
||||
<keyValuePair key="total_instances" value="9" description="" />
|
||||
<keyValuePair key="total_nets" value="0" description="" />
|
||||
<keyValuePair key="total_processes" value="37" description="" />
|
||||
<keyValuePair key="xilinx_hdl_libraries_used" value="secureip simprims_ver " description="" />
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</webTalkData>
|
||||
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Reference in New Issue
Block a user