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This commit is contained in:
goochey
2019-02-16 17:40:18 -05:00
parent faf9f883dd
commit 54cccd419f
107 changed files with 6032 additions and 121 deletions
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11
lab2CA.sim/sim_1/impl/func/xsim/alu_tb.tcl Normal file
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set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

927
lab2CA.sim/sim_1/impl/func/xsim/alu_tb_func_impl.v Normal file
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// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
// Date : Sat Feb 16 16:48:37 2019
// Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
// Command : write_verilog -mode funcsim -nolib -force -file
// C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/alu_tb_func_impl.v
// Design : RegFile
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k160tifbg484-2L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* ECO_CHECKSUM = "b4d7812f" *)
(* NotValidForBitStream *)
module RegFile
(clk,
reset,
write_index,
op0_idx,
op1_idx,
write_data,
op0,
op1);
input clk;
input reset;
input [1:0]write_index;
input [1:0]op0_idx;
input [1:0]op1_idx;
input [8:0]write_data;
output [8:0]op0;
output [8:0]op1;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire [8:0]op0;
wire [8:0]op0_OBUF;
wire \op0_OBUF[8]_inst_i_10_n_0 ;
wire \op0_OBUF[8]_inst_i_11_n_0 ;
wire \op0_OBUF[8]_inst_i_12_n_0 ;
wire \op0_OBUF[8]_inst_i_6_n_0 ;
wire \op0_OBUF[8]_inst_i_7_n_0 ;
wire \op0_OBUF[8]_inst_i_8_n_0 ;
wire \op0_OBUF[8]_inst_i_9_n_0 ;
wire [1:0]op0_idx;
wire [1:0]op0_idx_IBUF;
wire [8:0]op1;
wire [8:0]op1_OBUF;
wire [1:0]op1_idx;
wire [1:0]op1_idx_IBUF;
wire \r0/_n_0 ;
wire [8:0]r0_out;
wire [8:0]r1_out;
wire [8:0]r2_out;
wire [8:0]r3_out;
wire reset;
wire reset_IBUF;
wire [8:0]write_data;
wire [8:0]write_data_IBUF;
wire [1:0]write_index;
wire [1:0]write_index_IBUF;
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
mux_4_1 m0
(.op0_OBUF(op0_OBUF),
.op0_idx_IBUF(op0_idx_IBUF),
.r0_out(r0_out),
.r1_out(r1_out),
.r2_out(r2_out),
.r3_out(r3_out));
mux_4_1_0 m1
(.op1_OBUF(op1_OBUF),
.op1_idx_IBUF(op1_idx_IBUF),
.r0_out(r0_out),
.r1_out(r1_out),
.r2_out(r2_out),
.r3_out(r3_out));
OBUF \op0_OBUF[0]_inst
(.I(op0_OBUF[0]),
.O(op0[0]));
OBUF \op0_OBUF[1]_inst
(.I(op0_OBUF[1]),
.O(op0[1]));
OBUF \op0_OBUF[2]_inst
(.I(op0_OBUF[2]),
.O(op0[2]));
OBUF \op0_OBUF[3]_inst
(.I(op0_OBUF[3]),
.O(op0[3]));
OBUF \op0_OBUF[4]_inst
(.I(op0_OBUF[4]),
.O(op0[4]));
OBUF \op0_OBUF[5]_inst
(.I(op0_OBUF[5]),
.O(op0[5]));
OBUF \op0_OBUF[6]_inst
(.I(op0_OBUF[6]),
.O(op0[6]));
OBUF \op0_OBUF[7]_inst
(.I(op0_OBUF[7]),
.O(op0[7]));
OBUF \op0_OBUF[8]_inst
(.I(op0_OBUF[8]),
.O(op0[8]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h4))
\op0_OBUF[8]_inst_i_10
(.I0(write_index_IBUF[0]),
.I1(write_index_IBUF[1]),
.O(\op0_OBUF[8]_inst_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[8]_inst_i_11
(.I0(write_index_IBUF[0]),
.I1(write_index_IBUF[1]),
.O(\op0_OBUF[8]_inst_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h4))
\op0_OBUF[8]_inst_i_12
(.I0(write_index_IBUF[1]),
.I1(write_index_IBUF[0]),
.O(\op0_OBUF[8]_inst_i_12_n_0 ));
FDSE #(
.INIT(1'b1))
\op0_OBUF[8]_inst_i_6
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(\op0_OBUF[8]_inst_i_10_n_0 ),
.Q(\op0_OBUF[8]_inst_i_6_n_0 ),
.S(reset_IBUF));
FDSE #(
.INIT(1'b1))
\op0_OBUF[8]_inst_i_7
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(\r0/_n_0 ),
.Q(\op0_OBUF[8]_inst_i_7_n_0 ),
.S(reset_IBUF));
FDSE #(
.INIT(1'b1))
\op0_OBUF[8]_inst_i_8
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(\op0_OBUF[8]_inst_i_11_n_0 ),
.Q(\op0_OBUF[8]_inst_i_8_n_0 ),
.S(reset_IBUF));
FDSE #(
.INIT(1'b1))
\op0_OBUF[8]_inst_i_9
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(\op0_OBUF[8]_inst_i_12_n_0 ),
.Q(\op0_OBUF[8]_inst_i_9_n_0 ),
.S(reset_IBUF));
IBUF \op0_idx_IBUF[0]_inst
(.I(op0_idx[0]),
.O(op0_idx_IBUF[0]));
IBUF \op0_idx_IBUF[1]_inst
(.I(op0_idx[1]),
.O(op0_idx_IBUF[1]));
OBUF \op1_OBUF[0]_inst
(.I(op1_OBUF[0]),
.O(op1[0]));
OBUF \op1_OBUF[1]_inst
(.I(op1_OBUF[1]),
.O(op1[1]));
OBUF \op1_OBUF[2]_inst
(.I(op1_OBUF[2]),
.O(op1[2]));
OBUF \op1_OBUF[3]_inst
(.I(op1_OBUF[3]),
.O(op1[3]));
OBUF \op1_OBUF[4]_inst
(.I(op1_OBUF[4]),
.O(op1[4]));
OBUF \op1_OBUF[5]_inst
(.I(op1_OBUF[5]),
.O(op1[5]));
OBUF \op1_OBUF[6]_inst
(.I(op1_OBUF[6]),
.O(op1[6]));
OBUF \op1_OBUF[7]_inst
(.I(op1_OBUF[7]),
.O(op1[7]));
OBUF \op1_OBUF[8]_inst
(.I(op1_OBUF[8]),
.O(op1[8]));
IBUF \op1_idx_IBUF[0]_inst
(.I(op1_idx[0]),
.O(op1_idx_IBUF[0]));
IBUF \op1_idx_IBUF[1]_inst
(.I(op1_idx[1]),
.O(op1_idx_IBUF[1]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h1))
\r0/
(.I0(write_index_IBUF[0]),
.I1(write_index_IBUF[1]),
.O(\r0/_n_0 ));
register r3
(.clk_IBUF_BUFG(clk_IBUF_BUFG),
.\op0_OBUF[8]_inst_i_1 (\op0_OBUF[8]_inst_i_7_n_0 ),
.\op0_OBUF[8]_inst_i_1_0 (\op0_OBUF[8]_inst_i_6_n_0 ),
.\op0_OBUF[8]_inst_i_1_1 (\op0_OBUF[8]_inst_i_9_n_0 ),
.\op0_OBUF[8]_inst_i_1_2 (\op0_OBUF[8]_inst_i_8_n_0 ),
.r0_out(r0_out),
.r1_out(r1_out),
.r2_out(r2_out),
.r3_out(r3_out),
.reset_IBUF(reset_IBUF),
.write_data_IBUF(write_data_IBUF));
IBUF reset_IBUF_inst
(.I(reset),
.O(reset_IBUF));
IBUF \write_data_IBUF[0]_inst
(.I(write_data[0]),
.O(write_data_IBUF[0]));
IBUF \write_data_IBUF[1]_inst
(.I(write_data[1]),
.O(write_data_IBUF[1]));
IBUF \write_data_IBUF[2]_inst
(.I(write_data[2]),
.O(write_data_IBUF[2]));
IBUF \write_data_IBUF[3]_inst
(.I(write_data[3]),
.O(write_data_IBUF[3]));
IBUF \write_data_IBUF[4]_inst
(.I(write_data[4]),
.O(write_data_IBUF[4]));
IBUF \write_data_IBUF[5]_inst
(.I(write_data[5]),
.O(write_data_IBUF[5]));
IBUF \write_data_IBUF[6]_inst
(.I(write_data[6]),
.O(write_data_IBUF[6]));
IBUF \write_data_IBUF[7]_inst
(.I(write_data[7]),
.O(write_data_IBUF[7]));
IBUF \write_data_IBUF[8]_inst
(.I(write_data[8]),
.O(write_data_IBUF[8]));
IBUF \write_index_IBUF[0]_inst
(.I(write_index[0]),
.O(write_index_IBUF[0]));
IBUF \write_index_IBUF[1]_inst
(.I(write_index[1]),
.O(write_index_IBUF[1]));
endmodule
module mux_4_1
(op0_OBUF,
r1_out,
r0_out,
r3_out,
op0_idx_IBUF,
r2_out);
output [8:0]op0_OBUF;
input [8:0]r1_out;
input [8:0]r0_out;
input [8:0]r3_out;
input [1:0]op0_idx_IBUF;
input [8:0]r2_out;
wire [8:0]op0_OBUF;
wire [1:0]op0_idx_IBUF;
wire [8:0]r0_out;
wire [8:0]r1_out;
wire [8:0]r2_out;
wire [8:0]r3_out;
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op0_OBUF[0]_inst_i_1
(.I0(r1_out[0]),
.I1(r0_out[0]),
.I2(r3_out[0]),
.I3(op0_idx_IBUF[1]),
.I4(op0_idx_IBUF[0]),
.I5(r2_out[0]),
.O(op0_OBUF[0]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op0_OBUF[1]_inst_i_1
(.I0(r1_out[1]),
.I1(r0_out[1]),
.I2(r3_out[1]),
.I3(op0_idx_IBUF[1]),
.I4(op0_idx_IBUF[0]),
.I5(r2_out[1]),
.O(op0_OBUF[1]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op0_OBUF[2]_inst_i_1
(.I0(r1_out[2]),
.I1(r0_out[2]),
.I2(r3_out[2]),
.I3(op0_idx_IBUF[1]),
.I4(op0_idx_IBUF[0]),
.I5(r2_out[2]),
.O(op0_OBUF[2]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op0_OBUF[3]_inst_i_1
(.I0(r1_out[3]),
.I1(r0_out[3]),
.I2(r3_out[3]),
.I3(op0_idx_IBUF[1]),
.I4(op0_idx_IBUF[0]),
.I5(r2_out[3]),
.O(op0_OBUF[3]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op0_OBUF[4]_inst_i_1
(.I0(r1_out[4]),
.I1(r0_out[4]),
.I2(r3_out[4]),
.I3(op0_idx_IBUF[1]),
.I4(op0_idx_IBUF[0]),
.I5(r2_out[4]),
.O(op0_OBUF[4]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op0_OBUF[5]_inst_i_1
(.I0(r1_out[5]),
.I1(r0_out[5]),
.I2(r3_out[5]),
.I3(op0_idx_IBUF[1]),
.I4(op0_idx_IBUF[0]),
.I5(r2_out[5]),
.O(op0_OBUF[5]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op0_OBUF[6]_inst_i_1
(.I0(r1_out[6]),
.I1(r0_out[6]),
.I2(r3_out[6]),
.I3(op0_idx_IBUF[1]),
.I4(op0_idx_IBUF[0]),
.I5(r2_out[6]),
.O(op0_OBUF[6]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op0_OBUF[7]_inst_i_1
(.I0(r1_out[7]),
.I1(r0_out[7]),
.I2(r3_out[7]),
.I3(op0_idx_IBUF[1]),
.I4(op0_idx_IBUF[0]),
.I5(r2_out[7]),
.O(op0_OBUF[7]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op0_OBUF[8]_inst_i_1
(.I0(r1_out[8]),
.I1(r0_out[8]),
.I2(r3_out[8]),
.I3(op0_idx_IBUF[1]),
.I4(op0_idx_IBUF[0]),
.I5(r2_out[8]),
.O(op0_OBUF[8]));
endmodule
(* ORIG_REF_NAME = "mux_4_1" *)
module mux_4_1_0
(op1_OBUF,
r1_out,
r0_out,
r3_out,
op1_idx_IBUF,
r2_out);
output [8:0]op1_OBUF;
input [8:0]r1_out;
input [8:0]r0_out;
input [8:0]r3_out;
input [1:0]op1_idx_IBUF;
input [8:0]r2_out;
wire [8:0]op1_OBUF;
wire [1:0]op1_idx_IBUF;
wire [8:0]r0_out;
wire [8:0]r1_out;
wire [8:0]r2_out;
wire [8:0]r3_out;
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op1_OBUF[0]_inst_i_1
(.I0(r1_out[0]),
.I1(r0_out[0]),
.I2(r3_out[0]),
.I3(op1_idx_IBUF[1]),
.I4(op1_idx_IBUF[0]),
.I5(r2_out[0]),
.O(op1_OBUF[0]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op1_OBUF[1]_inst_i_1
(.I0(r1_out[1]),
.I1(r0_out[1]),
.I2(r3_out[1]),
.I3(op1_idx_IBUF[1]),
.I4(op1_idx_IBUF[0]),
.I5(r2_out[1]),
.O(op1_OBUF[1]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op1_OBUF[2]_inst_i_1
(.I0(r1_out[2]),
.I1(r0_out[2]),
.I2(r3_out[2]),
.I3(op1_idx_IBUF[1]),
.I4(op1_idx_IBUF[0]),
.I5(r2_out[2]),
.O(op1_OBUF[2]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op1_OBUF[3]_inst_i_1
(.I0(r1_out[3]),
.I1(r0_out[3]),
.I2(r3_out[3]),
.I3(op1_idx_IBUF[1]),
.I4(op1_idx_IBUF[0]),
.I5(r2_out[3]),
.O(op1_OBUF[3]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op1_OBUF[4]_inst_i_1
(.I0(r1_out[4]),
.I1(r0_out[4]),
.I2(r3_out[4]),
.I3(op1_idx_IBUF[1]),
.I4(op1_idx_IBUF[0]),
.I5(r2_out[4]),
.O(op1_OBUF[4]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op1_OBUF[5]_inst_i_1
(.I0(r1_out[5]),
.I1(r0_out[5]),
.I2(r3_out[5]),
.I3(op1_idx_IBUF[1]),
.I4(op1_idx_IBUF[0]),
.I5(r2_out[5]),
.O(op1_OBUF[5]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op1_OBUF[6]_inst_i_1
(.I0(r1_out[6]),
.I1(r0_out[6]),
.I2(r3_out[6]),
.I3(op1_idx_IBUF[1]),
.I4(op1_idx_IBUF[0]),
.I5(r2_out[6]),
.O(op1_OBUF[6]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op1_OBUF[7]_inst_i_1
(.I0(r1_out[7]),
.I1(r0_out[7]),
.I2(r3_out[7]),
.I3(op1_idx_IBUF[1]),
.I4(op1_idx_IBUF[0]),
.I5(r2_out[7]),
.O(op1_OBUF[7]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\op1_OBUF[8]_inst_i_1
(.I0(r1_out[8]),
.I1(r0_out[8]),
.I2(r3_out[8]),
.I3(op1_idx_IBUF[1]),
.I4(op1_idx_IBUF[0]),
.I5(r2_out[8]),
.O(op1_OBUF[8]));
endmodule
module register
(r0_out,
r1_out,
r2_out,
r3_out,
reset_IBUF,
write_data_IBUF,
clk_IBUF_BUFG,
\op0_OBUF[8]_inst_i_1 ,
\op0_OBUF[8]_inst_i_1_0 ,
\op0_OBUF[8]_inst_i_1_1 ,
\op0_OBUF[8]_inst_i_1_2 );
output [8:0]r0_out;
output [8:0]r1_out;
output [8:0]r2_out;
output [8:0]r3_out;
input reset_IBUF;
input [8:0]write_data_IBUF;
input clk_IBUF_BUFG;
input \op0_OBUF[8]_inst_i_1 ;
input \op0_OBUF[8]_inst_i_1_0 ;
input \op0_OBUF[8]_inst_i_1_1 ;
input \op0_OBUF[8]_inst_i_1_2 ;
wire \Dout_tristate_oe_reg_n_0_[0] ;
wire \Dout_tristate_oe_reg_n_0_[1] ;
wire \Dout_tristate_oe_reg_n_0_[2] ;
wire \Dout_tristate_oe_reg_n_0_[3] ;
wire \Dout_tristate_oe_reg_n_0_[4] ;
wire \Dout_tristate_oe_reg_n_0_[5] ;
wire \Dout_tristate_oe_reg_n_0_[6] ;
wire \Dout_tristate_oe_reg_n_0_[7] ;
wire \Dout_tristate_oe_reg_n_0_[8] ;
wire clk_IBUF_BUFG;
wire \op0_OBUF[8]_inst_i_1 ;
wire \op0_OBUF[8]_inst_i_1_0 ;
wire \op0_OBUF[8]_inst_i_1_1 ;
wire \op0_OBUF[8]_inst_i_1_2 ;
wire [8:0]r0_out;
wire [8:0]r1_out;
wire [8:0]r2_out;
wire [8:0]r3_out;
wire reset_IBUF;
wire [8:0]write_data_IBUF;
FDRE #(
.INIT(1'b0))
\Dout_tristate_oe_reg[0]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(write_data_IBUF[0]),
.Q(\Dout_tristate_oe_reg_n_0_[0] ),
.R(reset_IBUF));
FDRE #(
.INIT(1'b0))
\Dout_tristate_oe_reg[1]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(write_data_IBUF[1]),
.Q(\Dout_tristate_oe_reg_n_0_[1] ),
.R(reset_IBUF));
FDRE #(
.INIT(1'b0))
\Dout_tristate_oe_reg[2]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(write_data_IBUF[2]),
.Q(\Dout_tristate_oe_reg_n_0_[2] ),
.R(reset_IBUF));
FDRE #(
.INIT(1'b0))
\Dout_tristate_oe_reg[3]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(write_data_IBUF[3]),
.Q(\Dout_tristate_oe_reg_n_0_[3] ),
.R(reset_IBUF));
FDRE #(
.INIT(1'b0))
\Dout_tristate_oe_reg[4]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(write_data_IBUF[4]),
.Q(\Dout_tristate_oe_reg_n_0_[4] ),
.R(reset_IBUF));
FDRE #(
.INIT(1'b0))
\Dout_tristate_oe_reg[5]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(write_data_IBUF[5]),
.Q(\Dout_tristate_oe_reg_n_0_[5] ),
.R(reset_IBUF));
FDRE #(
.INIT(1'b0))
\Dout_tristate_oe_reg[6]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(write_data_IBUF[6]),
.Q(\Dout_tristate_oe_reg_n_0_[6] ),
.R(reset_IBUF));
FDRE #(
.INIT(1'b0))
\Dout_tristate_oe_reg[7]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(write_data_IBUF[7]),
.Q(\Dout_tristate_oe_reg_n_0_[7] ),
.R(reset_IBUF));
FDRE #(
.INIT(1'b0))
\Dout_tristate_oe_reg[8]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.D(write_data_IBUF[8]),
.Q(\Dout_tristate_oe_reg_n_0_[8] ),
.R(reset_IBUF));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[0]_inst_i_2
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
.I1(\op0_OBUF[8]_inst_i_1_0 ),
.O(r1_out[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[0]_inst_i_3
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
.I1(\op0_OBUF[8]_inst_i_1 ),
.O(r0_out[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[0]_inst_i_4
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
.I1(\op0_OBUF[8]_inst_i_1_2 ),
.O(r3_out[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[0]_inst_i_5
(.I0(\Dout_tristate_oe_reg_n_0_[0] ),
.I1(\op0_OBUF[8]_inst_i_1_1 ),
.O(r2_out[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[1]_inst_i_2
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
.I1(\op0_OBUF[8]_inst_i_1_0 ),
.O(r1_out[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[1]_inst_i_3
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
.I1(\op0_OBUF[8]_inst_i_1 ),
.O(r0_out[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[1]_inst_i_4
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
.I1(\op0_OBUF[8]_inst_i_1_2 ),
.O(r3_out[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[1]_inst_i_5
(.I0(\Dout_tristate_oe_reg_n_0_[1] ),
.I1(\op0_OBUF[8]_inst_i_1_1 ),
.O(r2_out[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[2]_inst_i_2
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
.I1(\op0_OBUF[8]_inst_i_1_0 ),
.O(r1_out[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[2]_inst_i_3
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
.I1(\op0_OBUF[8]_inst_i_1 ),
.O(r0_out[2]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[2]_inst_i_4
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
.I1(\op0_OBUF[8]_inst_i_1_2 ),
.O(r3_out[2]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[2]_inst_i_5
(.I0(\Dout_tristate_oe_reg_n_0_[2] ),
.I1(\op0_OBUF[8]_inst_i_1_1 ),
.O(r2_out[2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[3]_inst_i_2
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
.I1(\op0_OBUF[8]_inst_i_1_0 ),
.O(r1_out[3]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[3]_inst_i_3
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
.I1(\op0_OBUF[8]_inst_i_1 ),
.O(r0_out[3]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[3]_inst_i_4
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
.I1(\op0_OBUF[8]_inst_i_1_2 ),
.O(r3_out[3]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[3]_inst_i_5
(.I0(\Dout_tristate_oe_reg_n_0_[3] ),
.I1(\op0_OBUF[8]_inst_i_1_1 ),
.O(r2_out[3]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[4]_inst_i_2
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
.I1(\op0_OBUF[8]_inst_i_1_0 ),
.O(r1_out[4]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[4]_inst_i_3
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
.I1(\op0_OBUF[8]_inst_i_1 ),
.O(r0_out[4]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[4]_inst_i_4
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
.I1(\op0_OBUF[8]_inst_i_1_2 ),
.O(r3_out[4]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[4]_inst_i_5
(.I0(\Dout_tristate_oe_reg_n_0_[4] ),
.I1(\op0_OBUF[8]_inst_i_1_1 ),
.O(r2_out[4]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[5]_inst_i_2
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
.I1(\op0_OBUF[8]_inst_i_1_0 ),
.O(r1_out[5]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[5]_inst_i_3
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
.I1(\op0_OBUF[8]_inst_i_1 ),
.O(r0_out[5]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[5]_inst_i_4
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
.I1(\op0_OBUF[8]_inst_i_1_2 ),
.O(r3_out[5]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[5]_inst_i_5
(.I0(\Dout_tristate_oe_reg_n_0_[5] ),
.I1(\op0_OBUF[8]_inst_i_1_1 ),
.O(r2_out[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[6]_inst_i_2
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
.I1(\op0_OBUF[8]_inst_i_1_0 ),
.O(r1_out[6]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[6]_inst_i_3
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
.I1(\op0_OBUF[8]_inst_i_1 ),
.O(r0_out[6]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[6]_inst_i_4
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
.I1(\op0_OBUF[8]_inst_i_1_2 ),
.O(r3_out[6]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[6]_inst_i_5
(.I0(\Dout_tristate_oe_reg_n_0_[6] ),
.I1(\op0_OBUF[8]_inst_i_1_1 ),
.O(r2_out[6]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[7]_inst_i_2
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
.I1(\op0_OBUF[8]_inst_i_1_0 ),
.O(r1_out[7]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[7]_inst_i_3
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
.I1(\op0_OBUF[8]_inst_i_1 ),
.O(r0_out[7]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[7]_inst_i_4
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
.I1(\op0_OBUF[8]_inst_i_1_2 ),
.O(r3_out[7]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[7]_inst_i_5
(.I0(\Dout_tristate_oe_reg_n_0_[7] ),
.I1(\op0_OBUF[8]_inst_i_1_1 ),
.O(r2_out[7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[8]_inst_i_2
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
.I1(\op0_OBUF[8]_inst_i_1_0 ),
.O(r1_out[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[8]_inst_i_3
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
.I1(\op0_OBUF[8]_inst_i_1 ),
.O(r0_out[8]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[8]_inst_i_4
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
.I1(\op0_OBUF[8]_inst_i_1_2 ),
.O(r3_out[8]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h8))
\op0_OBUF[8]_inst_i_5
(.I0(\Dout_tristate_oe_reg_n_0_[8] ),
.I1(\op0_OBUF[8]_inst_i_1_1 ),
.O(r2_out[8]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif

8
lab2CA.sim/sim_1/impl/func/xsim/alu_tb_vlog.prj Normal file
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# compile verilog/system verilog design source files
verilog xil_defaultlib \
"alu_tb_func_impl.v" \
"../../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
"../../../../../lab2CA.srcs/sources_1/new/ALU.v" \
# Do not sort compile order
nosort

12
lab2CA.sim/sim_1/impl/func/xsim/webtalk.jou Normal file
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#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 16:48:49 2019
# Process ID: 940
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/webtalk/xsim_webtalk.tcl -notrace

BIN
lab2CA.sim/sim_1/impl/func/xsim/xelab.pb Normal file
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Binary file not shown.

1
lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/Compile_Options.txt Normal file
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@@ -0,0 +1 @@
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "alu_tb_func_impl" "xil_defaultlib.alu_tb" "xil_defaultlib.glbl" -log "elaborate.log"

1
lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/TempBreakPointFile.txt Normal file
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@@ -0,0 +1 @@
Breakpoint File Version 1.0

119
lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/obj/xsim_1.c Normal file
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@@ -0,0 +1,119 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_79(char*, char *);
extern void execute_181(char*, char *);
extern void execute_182(char*, char *);
extern void execute_183(char*, char *);
extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
extern void execute_180(char*, char *);
extern void execute_84(char*, char *);
extern void execute_85(char*, char *);
extern void execute_129(char*, char *);
extern void execute_102(char*, char *);
extern void execute_150(char*, char *);
extern void execute_159(char*, char *);
extern void execute_168(char*, char *);
extern void execute_177(char*, char *);
extern void execute_178(char*, char *);
extern void execute_78(char*, char *);
extern void execute_81(char*, char *);
extern void execute_82(char*, char *);
extern void execute_83(char*, char *);
extern void execute_184(char*, char *);
extern void execute_185(char*, char *);
extern void execute_186(char*, char *);
extern void execute_187(char*, char *);
extern void execute_188(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[25] = {(funcp)execute_79, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_180, (funcp)execute_84, (funcp)execute_85, (funcp)execute_129, (funcp)execute_102, (funcp)execute_150, (funcp)execute_159, (funcp)execute_168, (funcp)execute_177, (funcp)execute_178, (funcp)execute_78, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_184, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_188, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 25;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/alu_tb_func_impl/xsim.reloc", (void **)funcTab, 25);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/alu_tb_func_impl/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/alu_tb_func_impl/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/alu_tb_func_impl/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/alu_tb_func_impl/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/alu_tb_func_impl/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

54
lab2CA.sim/sim_1/impl/func/xsim/xsim.dir/alu_tb_func_impl/webtalk/usage_statistics_ext_xsim.xml Normal file
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@@ -0,0 +1,54 @@
<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sat Feb 16 16:48:49 2019'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2405991" description="" />
<keyValuePair key="date_generated" value="Sat Feb 16 16:48:47 2019" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
<keyValuePair key="project_iteration" value="1" description="" />
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
<keyValuePair key="route_design" value="FALSE" description="" />
<keyValuePair key="target_device" value="not_applicable" description="" />
<keyValuePair key="target_family" value="not_applicable" description="" />
<keyValuePair key="target_package" value="not_applicable" description="" />
<keyValuePair key="target_speed" value="not_applicable" description="" />
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
</section>
<section name="user_environment" level="1" order="2" description="">
<keyValuePair key="cpu_name" value="Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" description="" />
<keyValuePair key="cpu_speed" value="3492 MHz" description="" />
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
<keyValuePair key="system_ram" value="34.000 GB" description="" />
<keyValuePair key="total_processors" value="1" description="" />
</section>
<section name="vivado_usage" level="1" order="3" description="">
</section>
<section name="xsim" level="1" order="4" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="command" value="xelab" description="" />
<keyValuePair key="debug" value="typical" description="" />
<keyValuePair key="dpi_used" value="false" description="" />
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