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This commit is contained in:
goochey
2019-02-16 17:40:18 -05:00
parent faf9f883dd
commit 54cccd419f
107 changed files with 6032 additions and 121 deletions
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8
lab2CA.sim/sim_1/impl/timing/xsim/alu_tb_vlog.prj Normal file
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# compile verilog/system verilog design source files
verilog xil_defaultlib \
"alu_tb_time_impl.v" \
"../../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
"../../../../../lab2CA.srcs/sources_1/new/ALU.v" \
# Do not sort compile order
nosort