Lots

Lots

lab2CA.srcs/sources_1/new/ALU.v

@@ -61,3 +61,48 @@ module ALU(
         .out(result));
 
 endmodule
+
+//testbench
+//module alu_tb();
+//reg [8:0] a;
+//reg [8:0] b;
+//reg [2:0] c;
+//wire [8:0] d;
+
+//ALU alu0(
+//.operand0(a),
+//.operand1(b),
+//.opcode(c),
+//.result(d));
+    
+//    initial begin
+//    a = 9'b000000111;
+//    b = 9'b000111000;
+//    c = 3'b000;
+//    #5
+//    a = 9'b000011000;
+//    b = 9'b000011000;
+//    c = 3'b001;
+//    #5
+//    a = 9'b101010100;
+//    b = 9'b010101011;
+//    c = 3'b010;
+//    #5
+//    a = 9'b101010100;
+//    b = 9'b010101000;
+//    c = 3'b011;
+//    #5
+//    a = 9'b000110000;
+//    b = 9'b000111000;
+//    c = 3'b100;
+//    #5
+//    a = 9'b01011000;
+//    c = 3'b101;
+//    #5
+//    a = 9'b00001010;
+//    c = 3'b110;
+//    #5
+//    #5 $finish;
+
+//    end
+//endmodule