Lots

Lots

lab2CA.srcs/sources_1/new/RegFile.v

@@ -54,3 +54,82 @@ module RegFile(input wire clk, reset,
         .switch(op1_idx));
     
 endmodule
+
+//testbench
+module regFile_tb();
+reg [8:0] write_d;
+reg [1:0] w_idx, op0_idx, op1_idx;
+reg reset;
+wire [8:0] op0,op1;
+
+    reg clk;
+    initial begin
+        clk = 1'b0;
+    end
+    always begin
+        #5 clk = ~clk; // Period to be determined
+    end
+
+RegFile regFile0(
+.clk(clk),
+.reset(reset),
+.write_index(w_idx),
+.op0_idx(op0_idx),
+.op1_idx(op1_idx),
+.write_data(write_d),
+.op0(op0),
+.op1(op1));
+    
+    initial begin
+    reset = 0;
+    #5
+    reset = 1;
+    #5
+    reset = 0;
+    w_idx = 2'b00;
+    op0_idx = 2'b00;
+    op1_idx = 2'b00;
+    write_d = 9'b000000011;
+    #5
+    w_idx = 2'b01;
+    #5
+    w_idx = 2'b10;
+    #5
+    w_idx = 2'b11;
+    #5
+    reset = 0;
+    w_idx = 2'b00;
+    op0_idx = 2'b00;
+    op1_idx = 2'b00;
+    write_d = 9'b001111000;
+    #5
+    reset = 0;
+    w_idx = 2'b01;
+    op0_idx = 2'b00;
+    op1_idx = 2'b01;
+    write_d = 9'b000001111;
+    #5
+    reset = 0;
+    w_idx = 2'b10;
+    op0_idx = 2'b00;
+    op1_idx = 2'b10;
+    write_d = 9'b111000001;
+    #5
+    reset = 0;
+    w_idx = 2'b11;
+    op0_idx = 2'b11;
+    op1_idx = 2'b10;
+    write_d = 9'b100110001;
+    #5
+    reset = 1;
+    w_idx = 2'b00;
+    #5
+    w_idx = 2'b10;
+    #5
+    w_idx = 2'b01;
+    #5
+    w_idx = 2'b11;
+    #5 $finish;
+
+    end
+endmodule