fetch unit test

2019-02-20 11:31:25 -05:00
parent 54cccd419f
commit 6550b48599
33 changed files with 429 additions and 182 deletions
--- a/lab2CA.sim/sim_1/behav/xsim/fetchUnit_tb_vlog.prj
+++ b/lab2CA.sim/sim_1/behav/xsim/fetchUnit_tb_vlog.prj
@@ -0,0 +1,10 @@
+# compile verilog/system verilog design source files
+verilog xil_defaultlib  \
+"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
+"../../../../lab2CA.srcs/sources_1/new/FetchUnit.v" \
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort