fetch unit test

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -315,8 +315,8 @@ module mux_2_1(input wire switch,
            
     always @(A,B,switch) begin
         case (switch)
-            2'b00 : out = A;
-            2'b01 : out = B;
+            1'b0 : out = A;
+            1'b1 : out = B;
             default : out = 9'bxxxxxxxxx;
         endcase
     end

lab2CA.srcs/sources_1/new/FetchUnit.v

@@ -1,6 +1,7 @@
 `timescale 1ns / 1ps
 
-module FetchUnit(input wire clk, reset, op_idx,
+module FetchUnit(input wire clk, reset, 
+                 input wire [1:0] op_idx,
                  input wire [8:0] AddrIn,
                  output wire [8:0] AddrOut);
   
@@ -16,8 +17,8 @@ module FetchUnit(input wire clk, reset, op_idx,
     //Adds 1 to the program counter
     add_9bit PCAdder(
         .A(progC_out),
-        .B(1'b1),
-        .Cin(1'b0),
+        .B(9'b000000001),
+        .Cin(9'b000000000),
         .Sum(AddrOut));
         
     mux_2_1 PCmux(
@@ -27,4 +28,64 @@ module FetchUnit(input wire clk, reset, op_idx,
         .switch(op_idx));
         
         
-endmodule
+endmodule
+
+//testbench
+//module fetchUnit_tb();
+//reg [8:0] addr_in;
+//reg opidx;
+//reg reset;
+//wire [8:0] addr_out;
+
+//    reg clk;
+//    initial begin
+//        clk = 1'b0;
+//    end
+//    always begin
+//        #5 clk = ~clk; // Period to be determined
+//    end
+
+//FetchUnit fetchUnit0(
+//.clk(clk),
+//.reset(reset),
+//.op_idx(opidx),
+//.AddrIn(addr_in),
+//.AddrOut(addr_out));
+
+
+    
+//    initial begin
+//    reset = 0;
+//    opidx = 1'b1;
+//    addr_in = 0'b000000000;
+//    #5
+//    reset = 1;
+//    #5
+//    reset = 0;
+//    opidx = 1'b0;
+//    addr_in = 9'b000001111;
+//    #5
+//    #5
+//    addr_in = 9'b011000011;
+//    #5
+//    #5
+//    opidx = 1'b1;
+//    #5
+//    #5
+//    #5
+//    #5
+//    opidx = 1'b0;
+//    addr_in = 9'b000001111;
+//    #5
+//    #5
+//    addr_in = 9'b010010011;
+//    #5
+//    opidx = 1'b1;
+//    #5
+//    #5
+//    #5
+//    #5
+//    #5 $finish;
+
+//    end
+//endmodule

lab2CA.srcs/sources_1/new/RegFile.v

@@ -99,8 +99,8 @@ RegFile regFile0(
     #5
     reset = 0;
     w_idx = 2'b00;
-    op0_idx = 2'b00;
-    op1_idx = 2'b00;
+    op0_idx = 2'b10;
+    op1_idx = 2'b11;
     write_d = 9'b001111000;
     #5
     reset = 0;