fetch unit test

2019-02-20 11:31:25 -05:00
parent 54cccd419f
commit 6550b48599
33 changed files with 429 additions and 182 deletions
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -315,8 +315,8 @@ module mux_2_1(input wire switch,
           
    always @(A,B,switch) begin
        case (switch)
-            2'b00 : out = A;
-            2'b01 : out = B;
+            1'b0 : out = A;
+            1'b1 : out = B;
            default : out = 9'bxxxxxxxxx;
        endcase
    end