Framework of ALU is pretty much done
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10
lab2CA.xpr
10
lab2CA.xpr
@@ -3,7 +3,7 @@
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<!-- -->
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<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="39" Path="C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr">
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<Project Version="7" Minor="39" Path="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
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@@ -95,6 +95,14 @@
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sim_1/new/ALU.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="RegFile"/>
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