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Fixed a few syntax errors

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This commit is contained in:
WilliamMiceli
2019-02-15 15:40:20 -05:00
parent fd22d5c7e6
commit 9628b971d7
1 changed files with 63 additions and 63 deletions
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126
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -29,66 +29,66 @@ module adder_9bit(
wire C_add7;
adder_1bit add0(
.A(A[0])
.B(B[0])
.Cin(Cin)
.S(Sum[0])
.A(A[0]),
.B(B[0]),
.Cin(Cin),
.S(Sum[0]),
.Cout(C_add0));
adder_1bit add1(
.A(A[0])
.B(B[0])
.Cin(C_add0)
.S(Sum[0])
.A(A[1]),
.B(B[1]),
.Cin(C_add0),
.S(Sum[1]),
.Cout(C_add1));
adder_1bit add2(
.A(A[0])
.B(B[0])
.Cin(C_add1)
.S(Sum[0])
.A(A[2]),
.B(B[2]),
.Cin(C_add1),
.S(Sum[2]),
.Cout(C_add2));
adder_1bit add3(
.A(A[0])
.B(B[0])
.Cin(C_add2)
.S(Sum[0])
.A(A[3]),
.B(B[3]),
.Cin(C_add2),
.S(Sum[3]),
.Cout(C_add3));
adder_1bit add4(
.A(A[0])
.B(B[0])
.Cin(C_add3)
.S(Sum[0])
.A(A[4]),
.B(B[4]),
.Cin(C_add3),
.S(Sum[4]),
.Cout(C_add4));
adder_1bit add5(
.A(A[0])
.B(B[0])
.Cin(C_add4)
.S(Sum[0])
.A(A[5]),
.B(B[5]),
.Cin(C_add4),
.S(Sum[5]),
.Cout(C_add5));
adder_1bit add6(
.A(A[0])
.B(B[0])
.Cin(C_add5)
.S(Sum[0])
.A(A[6]),
.B(B[6]),
.Cin(C_add5),
.S(Sum[6]),
.Cout(C_add6));
adder_1bit add7(
.A(A[0])
.B(B[0])
.Cin(C_add6)
.S(Sum[0])
.A(A[7]),
.B(B[7]),
.Cin(C_add6),
.S(Sum[7]),
.Cout(C_add7));
adder_1bit add8(
.A(A[0])
.B(B[0])
.Cin(C_add7)
.S(Sum[0])
.A(A[8]),
.B(B[8]),
.Cin(C_add7),
.S(Sum[8]),
.Cout(Cout));
endmodule
@@ -108,48 +108,48 @@ module and_9bit(
output wire [8:0] C);
and_1bit and0(
.A(A[0])
.B(B[0])
.A(A[0]),
.B(B[0]),
.C(C[0]));
and_1bit and1(
.A(A[1])
.B(B[1])
.A(A[1]),
.B(B[1]),
.C(C[1]));
and_1bit and2(
.A(A[2])
.B(B[2])
.A(A[2]),
.B(B[2]),
.C(C[2]));
and_1bit and3(
.A(A[3])
.B(B[3])
.A(A[3]),
.B(B[3]),
.C(C[3]));
and_1bit and4(
.A(A[4])
.B(B[4])
.A(A[4]),
.B(B[4]),
.C(C[4]));
and_1bit and5(
.A(A[5])
.B(B[5])
.A(A[5]),
.B(B[5]),
.C(C[5]));
and_1bit and6(
.A(A[6])
.B(B[6])
.A(A[6]),
.B(B[6]),
.C(C[6]));
and_1bit and7(
.A(A[7])
.B(B[7])
.A(A[7]),
.B(B[7]),
.C(C[7]));
and_1bit and8(
.A(A[8])
.B(B[8])
.A(A[8]),
.B(B[8]),
.C(C[8]));
endmodule
@@ -226,39 +226,39 @@ module not_9bit(
output wire [8:0] B);
not_1bit not0(
.A(A[0])
.A(A[0]),
.B(B[0]));
not_1bit not1(
.A(A[1])
.A(A[1]),
.B(B[1]));
not_1bit not2(
.A(A[2])
.A(A[2]),
.B(B[2]));
not_1bit not3(
.A(A[3])
.A(A[3]),
.B(B[3]));
not_1bit not4(
.A(A[4])
.A(A[4]),
.B(B[4]));
not_1bit not5(
.A(A[5])
.A(A[5]),
.B(B[5]));
not_1bit not6(
.A(A[6])
.A(A[6]),
.B(B[6]));
not_1bit not7(
.A(A[7])
.A(A[7]),
.B(B[7]));
not_1bit not8(
.A(A[8])
.A(A[8]),
.B(B[8]));
endmodule