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WilliamMiceli
2019-02-21 15:09:00 -05:00
parent 82bcddf241
commit 6900e74405
13 changed files with 99 additions and 181 deletions
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104
lab2CA.srcs/sources_1/new/FetchUnit.v
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@@ -31,61 +31,61 @@ module FetchUnit(input wire clk, reset,
endmodule
//testbench
//module fetchUnit_tb();
//reg [8:0] addr_in;
//reg opidx;
//reg reset;
//wire [8:0] addr_out;
module fetchUnit_tb();
reg [8:0] addr_in;
reg opidx;
reg reset;
wire [8:0] addr_out;
// reg clk;
// initial begin
// clk = 1'b0;
// end
// always begin
// #5 clk = ~clk; // Period to be determined
// end
reg clk;
initial begin
clk = 1'b0;
end
always begin
#5 clk = ~clk; // Period to be determined
end
//FetchUnit fetchUnit0(
//.clk(clk),
//.reset(reset),
//.op_idx(opidx),
//.AddrIn(addr_in),
//.AddrOut(addr_out));
FetchUnit fetchUnit0(
.clk(clk),
.reset(reset),
.op_idx(opidx),
.AddrIn(addr_in),
.AddrOut(addr_out));
// initial begin
// reset = 0;
// opidx = 1'b1;
// addr_in = 0'b000000000;
// #5
// reset = 1;
// #5
// reset = 0;
// opidx = 1'b0;
// addr_in = 9'b000001111;
// #5
// #5
// addr_in = 9'b011000011;
// #5
// #5
// opidx = 1'b1;
// #5
// #5
// #5
// #5
// opidx = 1'b0;
// addr_in = 9'b000001111;
// #5
// #5
// addr_in = 9'b010010011;
// #5
// opidx = 1'b1;
// #5
// #5
// #5
// #5
// #5 $finish;
initial begin
reset = 0;
opidx = 1'b1;
addr_in = 0'b000000000;
#5
reset = 1;
#5
reset = 0;
opidx = 1'b0;
addr_in = 9'b000001111;
#5
#5
addr_in = 9'b011000011;
#5
#5
opidx = 1'b1;
#5
#5
#5
#5
opidx = 1'b0;
addr_in = 9'b000001111;
#5
#5
addr_in = 9'b010010011;
#5
opidx = 1'b1;
#5
#5
#5
#5
#5 $finish;
// end
//endmodule
end
endmodule