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Fixed indentations

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WilliamMiceli
2019-03-29 17:28:50 -04:00
parent 2479eefa00
commit 71c6c2ad55
1 changed files with 264 additions and 263 deletions
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527
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -8,269 +8,270 @@ module ControlUnit(
output reg [1:0] bank, output reg [1:0] bank,
output reg addi, mem, dataMemEn, RegEn, halt, link, js); output reg addi, mem, dataMemEn, RegEn, halt, link, js);
always @(instIn, functBit)begin always @(instIn, functBit)
case(instIn) begin
4'b0000: // Halt/NOP case(instIn)
begin 4'b0000: // Halt/NOP
halt <= 1'b1; begin
RegEn <= 1'b1; halt <= 1'b1;
FU <= 3'b001; // Disable Branching RegEn <= 1'b1;
addi <= 1'b0; FU <= 3'b001; // Disable Branching
dataMemEn <= 1'b0; // Disabled addi <= 1'b0;
aluOut <= 4'b0000; dataMemEn <= 1'b0; // Disabled
mem <= 1'b0; aluOut <= 4'b0000;
link <= 1'b0; mem <= 1'b0;
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b0001: // Load Byte end
begin 4'b0001: // Load Byte
aluOut <= 4'b0000; begin
mem <= 1'b1; aluOut <= 4'b0000;
dataMemEn <= 1'b0; // Disabled mem <= 1'b1;
RegEn <= 1'b0; dataMemEn <= 1'b0; // Disabled
FU <= 3'b001; // Disable Branching RegEn <= 1'b0;
addi <= 1'b0; FU <= 3'b001; // Disable Branching
halt <= 1'b0; addi <= 1'b0;
link <= 1'b0; halt <= 1'b0;
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b0010: // Store Byte end
begin 4'b0010: // Store Byte
aluOut <= 4'b0000; begin
mem <= 1'b0; aluOut <= 4'b0000;
dataMemEn <= 1'b1; // Enabled mem <= 1'b0;
RegEn <= 1'b1; dataMemEn <= 1'b1; // Enabled
FU <= 3'b001; // Disable Branching RegEn <= 1'b1;
halt <= 1'b0; FU <= 3'b001; // Disable Branching
addi <= 1'b0; halt <= 1'b0;
link <= 1'b0; addi <= 1'b0;
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b0011: // Link end
begin 4'b0011: // Link
halt <= 1'b0; begin
RegEn <= 1'b0; halt <= 1'b0;
FU <= 3'b001; RegEn <= 1'b0;
addi <= 1'b0; FU <= 3'b001;
aluOut <= 4'b0000; addi <= 1'b0;
mem <= 1'b0; aluOut <= 4'b0000;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b1; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b1;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b0100: // Zero end
begin 4'b0100: // Zero
aluOut <= 4'b1011; begin
RegEn <= 1'b0; aluOut <= 4'b1011;
FU <= 3'b001; // Disable Branching RegEn <= 1'b0;
halt <= 1'b0; FU <= 3'b001; // Disable Branching
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b0101: // Add/Subtract end
if(functBit == 1) begin // Subtract 4'b0101: // Add/Subtract
aluOut <= 4'b0001; if(functBit == 1) begin // Subtract
RegEn <= 1'b0; aluOut <= 4'b0001;
FU <= 3'b001; RegEn <= 1'b0;
halt <= 1'b0; FU <= 3'b001;
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
else begin // Add end
aluOut <= 4'b0000; else begin // Add
RegEn <= 1'b0; aluOut <= 4'b0000;
FU <= 3'b001; // Disable Branching RegEn <= 1'b0;
halt <= 1'b0; FU <= 3'b001; // Disable Branching
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b0110: // Add Immediate end
begin 4'b0110: // Add Immediate
aluOut <= 4'b1010; begin
addi <= 1'b1; aluOut <= 4'b1010;
RegEn <= 1'b0; addi <= 1'b1;
FU <= 3'b001; // Disable Branching RegEn <= 1'b0;
halt <= 1'b0; FU <= 3'b001; // Disable Branching
mem <= 1'b0; halt <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b0111: // Set if Less Than end
begin 4'b0111: // Set if Less Than
aluOut <= 4'b1001; begin
RegEn <= 1'b0; aluOut <= 4'b1001;
FU <= 3'b001; // Disable Branching RegEn <= 1'b0;
halt <= 1'b0; FU <= 3'b001; // Disable Branching
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b1000: // Jump to Register end
begin 4'b1000: // Jump to Register
aluOut <= 4'b0000; begin
FU <= 3'b000; aluOut <= 4'b0000;
RegEn <= 1'b1; FU <= 3'b000;
halt <= 1'b0; RegEn <= 1'b1;
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b1001: // Jump Forward end
begin 4'b1001: // Jump Forward
aluOut <= 4'b0000; begin
FU <= 3'b010; aluOut <= 4'b0000;
RegEn <= 1'b1; FU <= 3'b010;
halt <= 1'b0; RegEn <= 1'b1;
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b1010: // Bank Load/Bank Store end
begin 4'b1010: // Bank Load/Bank Store
halt <= 1'b0; begin
RegEn <= !functBit; halt <= 1'b0;
FU <= 3'b001; // Disable Branching RegEn <= !functBit;
addi <= 1'b0; FU <= 3'b001; // Disable Branching
aluOut <= 4'b0000; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled aluOut <= 4'b0000;
mem <= 1'b0; dataMemEn <= 1'b0; // Disabled
link <= 1'b0; mem <= 1'b0;
bank <= {functBit,functBit}; link <= 1'b0;
js <= 1'b0; bank <= {functBit,functBit};
end js <= 1'b0;
4'b1011: // Jump Backward end
begin 4'b1011: // Jump Backward
aluOut <= 4'b0000; begin
FU <= 3'b010; aluOut <= 4'b0000;
RegEn <= 1'b1; FU <= 3'b010;
halt <= 1'b0; RegEn <= 1'b1;
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b1; bank <= 2'b10;
end js <= 1'b1;
4'b1100: // Branch if Zero end
begin 4'b1100: // Branch if Zero
aluOut <= 4'b1010; begin
FU <= 3'b110; aluOut <= 4'b1010;
RegEn <= 1'b1; FU <= 3'b110;
halt <= 1'b0; RegEn <= 1'b1;
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b1101: // NOR end
begin 4'b1101: // NOR
aluOut <= 4'b0011; begin
RegEn <= 1'b0; aluOut <= 4'b0011;
FU <= 3'b001; // Disable Branching RegEn <= 1'b0;
halt <= 1'b0; FU <= 3'b001; // Disable Branching
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b1110: // OR/AND end
if(functBit == 1) // AND 4'b1110: // OR/AND
begin if(functBit == 1) // AND
aluOut <= 4'b0100; begin
RegEn <= 1'b0; aluOut <= 4'b0100;
FU <= 3'b001; // Disable Branching RegEn <= 1'b0;
halt <= 1'b0; FU <= 3'b001; // Disable Branching
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
else // OR end
begin else // OR
aluOut <= 4'b0010; begin
RegEn <= 1'b0; aluOut <= 4'b0010;
FU <= 3'b001; // Disable Branching RegEn <= 1'b0;
halt <= 1'b0; FU <= 3'b001; // Disable Branching
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
4'b1111: // Shift Right Logical/Shift Left Logical end
if(functBit == 1) // Shift Right Logical 4'b1111: // Shift Right Logical/Shift Left Logical
begin if(functBit == 1) // Shift Right Logical
aluOut <= 4'b0110; begin
RegEn <= 1'b0; aluOut <= 4'b0110;
FU <= 3'b001; // Disable Branching RegEn <= 1'b0;
halt <= 1'b0; FU <= 3'b001; // Disable Branching
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
else // Shift Left Logical end
begin else // Shift Left Logical
aluOut <= 4'b0101; begin
RegEn <= 1'b0; aluOut <= 4'b0101;
FU <= 3'b001; // Disable Branching RegEn <= 1'b0;
halt <= 1'b0; FU <= 3'b001; // Disable Branching
addi <= 1'b0; halt <= 1'b0;
mem <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled mem <= 1'b0;
link <= 1'b0; dataMemEn <= 1'b0; // Disabled
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
default: end
begin default:
halt <= 1'b1; begin
RegEn <= 1'b1; halt <= 1'b1;
FU <= 3'b001; RegEn <= 1'b1;
dataMemEn <= 1'b0; // Disabled FU <= 3'b001;
addi <= 1'b0; dataMemEn <= 1'b0; // Disabled
aluOut <= 4'b0000; addi <= 1'b0;
mem <= 1'b0; aluOut <= 4'b0000;
link <= 1'b0; mem <= 1'b0;
bank <= 2'b10; link <= 1'b0;
js <= 1'b0; bank <= 2'b10;
end js <= 1'b0;
end
endcase endcase
end end
endmodule endmodule