Modularized project; mux, clock, and reg done; Progress on RegFile

lab2CA.srcs/sources_1/new/BasicModules.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 02/15/2019 12:18:27 PM
+// Design Name: 
+// Module Name: BasicModules
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module BasicModules();
+endmodule
+
+module gen_clock();
+
+    reg clk;
+    
+    initial begin
+        clk = 1'b0;
+    end
+    
+    always begin
+        #5 clk = ~clk; // Period to be determined
+    end
+
+endmodule
+
+module register(input wire clk, reset,
+                input wire [1:0] En,
+                input wire [8:0] Din,
+                output reg [8:0] Dout);
+                
+    always @(posedge clk) begin
+        if (reset == 1'b1) begin
+            Dout <= 9'b000000000;
+        end
+        else if (En == 2'b00) begin
+            Dout <= Din;
+        end
+        else begin
+            Dout <= "ZZZZZZZZZ";
+        end
+    end
+
+endmodule
+
+module mux(input wire [1:0] switch,
+           input wire [8:0] A,B,C,D,
+           output reg [8:0] out);
+           
+    always @(A,B,C,D,switch) begin
+        if (switch == 2'b00) begin
+            out = A;
+        end
+        else if (switch == 2'b01) begin
+            out = B;
+        end
+        else if (switch == 2'b11) begin
+            out = C;
+        end
+        else begin
+            out = D;
+        end
+    end
+
+endmodule
+